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Networks on Chips: Technology and Tools

Book Description

The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.

Table of Contents

  1. Copyright
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. About the Authors
  4. List of Contributors
  5. 1. Networks on Chip
    1. 1.1. Why On-Chip Networking?
    2. 1.2. Technology Trends
      1. 1.2.1. Signal Integrity
      2. 1.2.2. Reliability
      3. 1.2.3. Non-determinism in SoC Modeling and Design
      4. 1.2.4. Variability, Design Methodologies and NoCs
    3. 1.3. SoC Objectives and NoC Needs
      1. 1.3.1. Some Design Examples
      2. 1.3.2. Distinguishing Characteristics of NoCs
    4. 1.4. Once Over Lightly
      1. 1.4.1. NoC Architectures
      2. 1.4.2. Physical Layer
      3. 1.4.3. Data-Link Layer
      4. 1.4.4. Network and Transport Layers
      5. 1.4.5. Software Layers
      6. 1.4.6. NoC Design Tools and Design Examples
    5. 1.5. Perspectives
    6. References
      1.  
  6. 2. Network Architecture: Principles and Examples
    1. 2.1. Network Architecture
      1. 2.1.1. Shared-Medium Networks
      2. 2.1.2. Direct Networks
      3. 2.1.3. Indirect Networks
      4. 2.1.4. Hybrid Networks
    2. 2.2. Network Architectures for On-Chip Realization
    3. 2.3. Ad Hoc Network Architectures
    4. 2.4. Component Design for NoCs
      1. 2.4.1. Switch Design
      2. 2.4.2. Link Design
      3. 2.4.3. NI Design
    5. 2.5. Properties of Network Architectures
    6. 2.6. Summary
    7. References
      1.  
  7. 3. Physical Network Layer
    1. 3.1. Interconnection in DSM SoC
      1. 3.1.1. Interconnection Models
      2. 3.1.2. Signal Integrity and Noises on the Interconnect
      3. 3.1.3. Issues in Power and Clock Distribution
    2. 3.2. High-Performance Signaling
      1. 3.2.1. High-Speed Signaling
        1. Voltage-mode signaling
        2. Current-mode signaling
        3. Wave-pipelining
      2. 3.2.2. Low-Power Interconnection Design
        1. Channel coding to reduce the switching probability
        2. Wire capacitance reducing techniques
        3. Low-swing signaling
          1. Driver circuits
          2. Receiver circuits
          3. Static and dynamic wires
          4. Optimal voltage swing
        4. Frequency/voltage scaling
      3. 3.2.3. Synchronization
        1. Clock distribution inside an NoC
        2. Synchronizers
    3. 3.3. Building Blocks
      1. 3.3.1. Switch Design
        1. Switch fabric
        2. Switch scheduler
      2. 3.3.2. Queuing Buffer and Memory Design
      3. 3.3.3. Size Determination of Physical Transfer unit
        1. Size of physical transfer unit
        2. On-chip serialization
        3. Serializer/deserializer circuits
    4. 3.4. Summary
    5. References
      1.  
  8. 4. The Data-Link Layer in NoC Design
    1. 4.1. Tasks of the Data-Link Layer
    2. 4.2. On-Chip Communication Reliability
    3. 4.3. Fault Models for NoCs
      1. 4.3.1. Bit Error Rate Model
      2. 4.3.2. New Fault Model Notations
      3. 4.3.3. Stochastic Failure Model
    4. 4.4. Principles of Coding Theory
      1. 4.4.1. Linear Block Codes
        1. Syndromes
        2. Standard array decoding
        3. Syndrome decoding
      2. 4.4.2. Hamming Codes
      3. 4.4.3. Cyclic Codes
        1. Generator polynomial
        2. Burst errors
      4. 4.4.4. Cyclic Redundancy Check
      5. 4.4.5. Implementation of Hamming Codecs
      6. 4.4.6. Implementation of Cyclic Codecs
    5. 4.5. The Power-Reliability Trade-Off
      1. 4.5.1. Conflicting Requirements on Voltage Swing
      2. 4.5.2. Conflicting Requirements on Switching Activity
    6. 4.6. Unified Coding Framework
    7. 4.7. Adaptive Error Protection
      1. 4.7.1. Self-Calibrating NoCs
      2. 4.7.2. Coding Adaptation
    8. 4.8. Data-Link Layer Architecture: Case Studies
      1. 4.8.1. Micro-Modem
      2. 4.8.2. Nostrum
    9. 4.9. On-Chip Stochastic Communication
    10. 4.10. Link-Level versus End-to-End Error Protection
    11. 4.11. Flow Control
      1. 4.11.1. Flow Control Protocols
    12. 4.12. Performance Exploration
      1. 4.12.1. Considerations
    13. 4.13. Summary
    14. References
      1.  
  9. 5. Network and Transport Layers in Networks on Chip
    1. 5.1. Network and Transport Layers in NoCs
      1. 5.1.1. Classifying NoC Models
        1. ASIC
        2. ASSP and platforms
        3. FPGAs
        4. CMPs
    2. 5.2. NoC QoS
      1. 5.2.1. Traffic Classes and Service Classes
        1. Traffic classes and service classes in computer networks
        2. Traffic classes and service classes in NoCs
    3. 5.3. NoC Topology
      1. NoC types and topologies
    4. 5.4. Switching Techniques
      1. 5.4.1. Circuit Switching
        1. Virtual channels and virtual circuits
          1. Virtual circuits with multiple buffers per link
          2. Virtual circuits with a single buffer per link
        2. Circuit management
      2. 5.4.2. Packet Switching
        1. SAF switching
        2. VCT switching
        3. WH switching
      3. 5.4.3. Combinations of Different Switching Techniques
    5. 5.5. NoC Addressing and Routing
    6. 5.6. NoC Addressing
      1. 5.6.1. NoC Routing
        1. Static and dynamic routing
        2. Distributed and source routing
        3. Minimal and non-minimal routing
      2. 5.6.2. Deadlock
        1. Deadlock avoidance
      3. 5.6.3. NoC Dynamic Routing Schemes
    7. 5.7. Congestion Control and Flow Control
      1. 5.7.1. Congestion Control
        1. Congestion control without resource reservations
        2. Congestion control with resource reservations
      2. 5.7.2. Flow Control
      3. 5.7.3. Congestion Control and Flow Control for QoS
    8. 5.8. Summary
    9. References
      1.  
  10. 6. Network Interface Architecture and Design Issues
    1. 6.1. NI Services
      1. 6.1.1. Adaptation Services
        1. Core interfacing
        2. Packetization
      2. 6.1.2. Clock Adaptation
        1. Bandwidth and latency guarantees
      3. 6.1.3. Network Services
        1. Transactions ordering
        2. Reliable transactions
        3. Flow control
      4. 6.1.4. Functional Services
        1. Cache coherence
        2. Security
        3. Low power
    2. 6.2. NI Structure
    3. 6.3. Evolution of Communication Protocols
      1. 6.3.1. Considerations
    4. 6.4. Point-to-Point Communication Protocols
      1. 6.4.1. AXI Overview
        1. Advanced options
      2. 6.4.2. OCP Overview
        1. Bus bridge
        2. Processor interface
        3. Memory subsystem
        4. Signals common to each example
      3. 6.4.3. Bus versus Network Semantics
        1. Programming model
        2. Transaction ordering
        3. Atomic chains of transactions
        4. Deadlock
        5. Media arbitration
        6. Destination name and routing
        7. Latency
        8. Data format
        9. Buffering and flow control
    5. 6.5. Latest Advances in Processor Interfaces
    6. 6.6. The Packetization Stage
      1. 6.6.1. Hardware–Software Implementation
        1. Software library for packetization
        2. On-core module for packetizing
        3. Wrapper logic for packetizing
        4. Comparison
      2. 6.6.2. Packet Types
      3. 6.6.3. Impact of Packet Size
      4. 6.6.4. Impact of Flit Size
    7. 6.7. End-to-End Flow Control
    8. 6.8. Packet and Circuit Switching
    9. 6.9. NI Architecture: The Aethereal Case Study
      1. 6.9.1. NI Kernel Architecture
      2. 6.9.2. NI Shell Architecture
      3. 6.9.3. Network Configuration
      4. 6.9.4. NI Configuration
      5. 6.9.5. Implementation
      6. 6.9.6. NI and the Rest of the System
    10. 6.10. NI Architecture: The xpipes Case Study
      1. 6.10.1. The NI and the Rest of the System
    11. 6.11. NIs for Asynchronous NoCs: The Mango Case Study
      1. 6.11.1. Implementation Results
    12. 6.12. Summary
    13. References
      1.  
  11. 7. NoC Programming
    1. 7.1. Architectural Template
      1. 7.1.1. Shared Memory MPSIM
      2. 7.1.2. Message-Oriented Distributed Memory MPSIM
      3. 7.1.3. Memory Abstraction Implications on Interconnect Architecture
    2. 7.2. Task-Level Parallel Programming
      1. 7.2.1. Message Passing
        1. Message-passing implementation in MPSoCs
        2. Programming a message-passing NoC platform
        3. Message-passing performance analysis
      2. 7.2.2. Shared memory
        1. Shared-memory in MPSoCs
        2. Programming a shared-memory NoC platform
        3. Shared-memory performance analysis
    3. 7.3. Communication-Exposed Programming
      1. 7.3.1. Graphical dataflow programming environments
      2. 7.3.2. Stream Languages
        1. A case study: StreamIt
    4. 7.4. Computer-Aided Software Development Tools
      1. 7.4.1. Compilation
        1. Coarse-grain parallelism extraction
      2. 7.4.2. Testing and debugging
    5. 7.5. Summary
    6. References
      1.  
  12. 8. Design Methodologies and CAD Tool Flows for NoCs
    1. 8.1. Network Analysis and Simulation
      1. 8.1.1. NoC Modeling Environments
        1. The MPARM environment
        2. NoC emulation
      2. 8.1.2. Application Traffic Models
    2. 8.2. Network Synthesis and Optimization
      1. 8.2.1. NoC Architecture Exploration
      2. 8.2.2. NoC Instantiation
    3. 8.3. Design Flows for NoCs
      1. 8.3.1. NetChip
        1. Sunmap
        2. Sunfloor
          1. xpipes
      2. 8.3.2. Æthereal Design Flow
      3. 8.3.3. Input Specification
        1. NoC generation and configuration
        2. NoC verification
        3. NoC simulation
    4. 8.4. Tool Kits for Designing Bus-Based Interconnect
      1. 8.4.1. Silicon Backplane and Sonics Studio
      2. 8.4.2. STMicroelectronics STBus
        1. Basics on the STBus
        2. STBusGenKit
        3. The SLD tool
        4. The SD tool
      3. 8.4.3. Arteris
    5. 8.5. Summary
    6. References
      1.  
  13. 9. Designs and Implementations of NoC-Based SoCs
    1. 9.1. KAIST BONE Series
      1. 9.1.1. BONE-1: Prototype of On-Chip Network (PROTON)
        1. Overall architecture
        2. Packet routing scheme
        3. Off-chip connectivity
      2. 9.1.2. BONE-2: Low-Power NoC and Network-in-Package for Multimedia SoC Applications
        1. Topology selection
        2. Signal synchronization and serialization
        3. Low-swing signaling on global links
        4. Crossbar partial activation technique
        5. Low-energy coding on on-chip serial link
        6. Operating frequency scaling
        7. Design flow and methodology
        8. Chip implementation
        9. Networks-in-package
        10. Measurements and demonstration of system operation
        11. BONE-2 chip summary
      3. 9.1.3. BONE-3
        1. Supply-voltage-dependent reference voltage
        2. Self-calibrating phase difference
        3. Adaptive link bandwidth control
      4. 9.1.4. FONE: Flexible On-Chip Network
        1. NoC evaluation platform
        2. NoC run-time traffic monitoring system
        3. Case study: portable multimedia system
          1. Target system description
          2. NoC evaluation
          3. NoC optimization
        4. FONE platform summary
    2. 9.2. NoC-Based Experimental Systems
      1. 9.2.1. Pleiades: Heterogeneous Reconfigurable Processor for Baseband Wireless Application
      2. 9.2.2. Raw Machine: Scalable Multiprocessor Architecture
      3. 9.2.3. Multi-Context Network Using Flash-EEPROM Switches and Elastic Interconnects
    3. 9.3. Summary
    4. References
      1.