Book description
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution.This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.
* Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends
* An integrated presentation not currently available in any other book
* A thorough introduction to current design methodologies and chips designed with NoCs
Table of contents
- Copyright
- The Morgan Kaufmann Series in Systems on Silicon
- About the Authors
- List of Contributors
- 1. Networks on Chip
- 2. Network Architecture: Principles and Examples
- 3. Physical Network Layer
-
4. The Data-Link Layer in NoC Design
- 4.1. Tasks of the Data-Link Layer
- 4.2. On-Chip Communication Reliability
- 4.3. Fault Models for NoCs
- 4.4. Principles of Coding Theory
- 4.5. The Power-Reliability Trade-Off
- 4.6. Unified Coding Framework
- 4.7. Adaptive Error Protection
- 4.8. Data-Link Layer Architecture: Case Studies
- 4.9. On-Chip Stochastic Communication
- 4.10. Link-Level versus End-to-End Error Protection
- 4.11. Flow Control
- 4.12. Performance Exploration
- 4.13. Summary
- References
- 5. Network and Transport Layers in Networks on Chip
-
6. Network Interface Architecture and Design Issues
- 6.1. NI Services
- 6.2. NI Structure
- 6.3. Evolution of Communication Protocols
- 6.4. Point-to-Point Communication Protocols
- 6.5. Latest Advances in Processor Interfaces
- 6.6. The Packetization Stage
- 6.7. End-to-End Flow Control
- 6.8. Packet and Circuit Switching
- 6.9. NI Architecture: The Aethereal Case Study
- 6.10. NI Architecture: The xpipes Case Study
- 6.11. NIs for Asynchronous NoCs: The Mango Case Study
- 6.12. Summary
- References
- 7. NoC Programming
- 8. Design Methodologies and CAD Tool Flows for NoCs
-
9. Designs and Implementations of NoC-Based SoCs
-
9.1. KAIST BONE Series
- 9.1.1. BONE-1: Prototype of On-Chip Network (PROTON)
-
9.1.2. BONE-2: Low-Power NoC and Network-in-Package for Multimedia SoC Applications
- Topology selection
- Signal synchronization and serialization
- Low-swing signaling on global links
- Crossbar partial activation technique
- Low-energy coding on on-chip serial link
- Operating frequency scaling
- Design flow and methodology
- Chip implementation
- Networks-in-package
- Measurements and demonstration of system operation
- BONE-2 chip summary
- 9.1.3. BONE-3
- 9.1.4. FONE: Flexible On-Chip Network
- 9.2. NoC-Based Experimental Systems
- 9.3. Summary
- References
-
9.1. KAIST BONE Series
Product information
- Title: Networks on Chips
- Author(s):
- Release date: August 2006
- Publisher(s): Morgan Kaufmann
- ISBN: 9780080473567
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