Networks-on-Chip

Introduction

The logic implementations of a network-on-chip (NoC) directly determine its overhead, performance, and efficiency. The network latency depends on router pipeline delays; a primary design goal of router architectures is to reduce pipeline delays in a low-cost way. Buffers consume a significant portion of NoC power and area budgets. Dynamically sharing buffers among virtual channels (VCs) or ports can reduce buffer amount requirements, while maintaining or improving performance. Also, avoiding network congestion is essential to optimize the throughput and latency. Efficiently supporting multicast or broadcast communications is important for the overall performance of many-core systems. While packet switching networks are appropriate ...