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Networks-on-Chip

Book Description

Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.

This textbook is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. Graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. Industrial engineers can refer to this book to make practical tradeoffs as well. Graduates and engineers who focus on off-chip network design can also refer to this book to achieve deadlock-free routing algorithm designs.



  • Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.
  • The coherent and uniform format offers readers a clear, quick and efficient exploration of NoC design space
  • Covers many novel and exciting research ideas, which encourage researchers to further delve into these topics.
  • Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Preface
  6. About the Editor-in-Chief and Authors
    1. Editor-in-Chief
    2. Authors
  7. Part I: Prologue
    1. Chapter 1: Introduction
      1. Abstract
      2. 1.1 The dawn of the many-core era
      3. 1.2 Communication-centric cross-layer optimizations
      4. 1.3 A baseline design space exploration of NoCs
      5. 1.4 Review of NoC research
      6. 1.5 Trends of real processors
      7. 1.6 Overview of the book
  8. Part II: Logic implementations
    1. Introduction
    2. Chapter 2: A single-cycle router with wing channels
      1. Abstract
      2. 2.1 Introduction
      3. 2.2 The router architecture
      4. 2.3 Microarchitecture designs
      5. 2.4 Experimental results
      6. 2.5 Chapter summary
    3. Chapter 3: Dynamic virtual channel routers with congestion awareness
      1. Abstract
      2. 3.1 Introduction
      3. 3.2 DVC with congestion awareness
      4. 3.3 Multiple-port shared buffer with congestion awareness
      5. 3.4 DVC router microarchitecture
      6. 3.5 HiBB router microarchitecture
      7. 3.6 Evaluation
      8. 3.7 Chapter Summary
    4. Chapter 4: Virtual bus structure-based network-on-chip topologies
      1. Abstract
      2. 4.1 Introduction
      3. 4.2 Background
      4. 4.3 Motivation
      5. 4.4 The VBON
      6. 4.5 Evaluation
      7. 4.6 Chapter summary
  9. Part III: Routing and flow control
    1. Introduction
    2. Chapter 5: Routing algorithms for workload consolidation
      1. Abstract
      2. 5.1 Introduction
      3. 5.2 Background
      4. 5.3 Motivation
      5. 5.4 Destination-based adaptive routing
      6. 5.5 Evaluation
      7. 5.6 Analysis and discussion
      8. 5.7 Chapter summary
    3. Chapter 6: Flow control for fully adaptive routing
      1. Abstract
      2. 6.1 Introduction
      3. 6.2 Background
      4. 6.3 Motivation
      5. 6.4 Flow control and routing designs
      6. 6.5 Evaluation on synthetic traffic
      7. 6.6 Evaluation of parsec workloads
      8. 6.7 Detailed analysis of flow control
      9. 6.8 Further discussion
      10. 6.9 Chapter summary
      11. Appendix: logical equivalence of <span xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops" class="italic">Alg</span> and and <span xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops" class="italic">Alg</span> + + <span xmlns="http://www.w3.org/1999/xhtml" xmlns:epub="http://www.idpf.org/2007/ops" class="italic">WPF</span>
    4. Chapter 7: Deadlock-free flow control for torus networks-on-chip
      1. Abstract
      2. 7.1 Introduction
      3. 7.2 Limitations of existing designs
      4. 7.3 Flit bubble flow control
      5. 7.4 Router microarchitecture
      6. 7.5 Methodology
      7. 7.6 Evaluation on 1D tori (rings)
      8. 7.7 Evaluation on 2D tori
      9. 7.8 Overheads: power and area
      10. 7.9 Discussion and related work
      11. 7.10 Chapter summary
  10. Part IV: Programming paradigms
    1. Introduction
    2. Chapter 8: Supporting cache-coherent collective communications
      1. Abstract
      2. 8.1 Introduction
      3. 8.2 Message combination framework
      4. 8.3 Bam routing
      5. 8.4 Router pipeline and microarchitecture
      6. 8.5 Evaluation
      7. 8.6 Power analysis
      8. 8.7 Related work
      9. 8.8 Chapter summary
    3. Chapter 9: Network-on-chip customizations for message passing interface primitives
      1. Abstract
      2. 9.1 Introduction
      3. 9.2 Background
      4. 9.3 Motivation
      5. 9.4 Communication customization architectures
      6. 9.5 Evaluation
      7. 9.6 Chapter summary
    4. Chapter 10: Message passing interface communication protocol optimizations
      1. Abstract
      2. 10.1 Introduction
      3. 10.2 Background
      4. 10.3 Motivation
      5. 10.4 Adaptive communication mechanisms
      6. 10.5 Evaluation
      7. 10.6 Chapter summary
  11. Part V: Epilogue
    1. Chapter 11: Conclusions and future work
      1. Abstract
      2. 11.1 Conclusions
      3. 11.2 Future work
  12. Index