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Network Processors

Book Description

Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. This book leads the reader through the requirements and the underlying theory of networks, network processing, and network processors. It covers implementation of network processors and intergrates EZchip Microcode Development Environment so that you can gain hands-on experience in writing high-speed networking applications. By the end of the book, the reader will be able to write and test applications on a simulated network processor.

  • Comprehensive, theoretical, and pracitical coverage of networks and high-speed networking applications
  • Descirbes contemporary core, metro, and access networks and their processing algorithms
  • Covers network processor architectures and programming models, enabling readers to assess the optimal network processor typer and configuration for their application
  • Free download from http://www.cse.bgu.ac.il/npbook includes microcode development tools that provide hands-on experience with programming a network processor

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. The Morgan Kaufmann Series in Systems on Silicon
  5. Copyright
  6. Dedication
  7. Preface
  8. Acknowledgments
  9. Chapter 1: Introduction and Motivation
    1. 1.1 NETWORK PROCESSORS ECOSYSTEM
    2. 1.2 COMMUNICATION SYSTEMS AND APPLICATIONS
    3. 1.3 NETWORK ELEMENTS
    4. 1.4 NETWORK PROCESSORS
    5. 1.5 STRUCTURE OF THIS BOOK
    6. 1.6 SUMMARY
  10. PART 1: Networks
    1. Introduction to Networks
    2. Chapter 2: Networking Fundamentals
      1. 2.1 INTRODUCTION
      2. 2.2 NETWORKS PRIMER
      3. 2.3 DATA NETWORKING MODELS
      4. 2.4 BASIC NETWORK TECHNOLOGIES
      5. 2.5 TELECOM NETWORKS
      6. 2.6 DATA NETWORKS
      7. 2.7 SUMMARY
    3. Chapter 3: Converged Networks
      1. 3.1 INTRODUCTION
      2. 3.2 FROM TELECOM NETWORKS TO DATA NETWORKS
      3. 3.3 FROM DATACOM TO TELECOM
      4. 3.4 SUMMARY
    4. Chapter 4: Access and Home Networks
      1. 4.1 ACCESS NETWORKS
      2. 4.2 HOME AND BUILDING NETWORKS
      3. 4.3 SUMMARY
  11. PART 2: Processing
    1. Introduction to Processing
    2. Chapter 5: Packet Processing
      1. 5.1 INTRODUCTION AND DEFINITIONS
      2. 5.2 INGRESS AND EGRESS
      3. 5.3 FRAMING
      4. 5.4 PARSING AND CLASSIFICATION
      5. 5.5 SEARCH, LOOKUP, AND FORWARDING
      6. 5.6 MODIFICATION
      7. 5.7 COMPRESSION AND ENCRYPTION
      8. 5.8 QUEUEING AND TRAFFIC MANAGEMENT
      9. 5.9 SUMMARY
    3. Chapter 6: Packet Flow Handling
      1. 6.1 DEFINITIONS
      2. 6.2 QUALITY OF SERVICE
      3. 6.3 CLASS OF SERVICE
      4. 6.4 QoS MECHANISMS
      5. 6.5 SUMMARY
    4. Chapter 7: Architecture
      1. 7.1 INTRODUCTION
      2. 7.2 BACKGROUND AND DEFINITIONS
      3. 7.3 EQUIPMENT DESIGN ALTERNATIVES: ASICS VERSUS NP
      4. 7.4 NETWORK PROCESSORS BASIC ARCHITECTURES
      5. 7.5 INSTRUCTION SET (SCALABILITY; PROCESSING SPEED)
      6. 7.6 NP COMPONENTS
      7. 7.7 SUMMARY
    5. Chapter 8: Software
      1. 8.1 INTRODUCTION
      2. 8.2 CONVENTIONAL SYSTEMS
      3. 8.3 PROGRAMMING MODELS CLASSIFICATION
      4. 8.4 PARALLEL PROGRAMMING
      5. 8.5 PIPELINING
      6. 8.6 NETWORK PROCESSOR PROGRAMMING
      7. 8.7 SUMMARY
    6. Chapter 9: NP Peripherals
      1. 9.1 SWITCH FABRICS
      2. 9.2 COPROCESSORS
      3. 9.3 SUMMARY
  12. PART 3: A Network Processor: EZchip
    1. Introduction to A Network Processor: EZchip
    2. Chapter 10: EZchip Architecture, Capabilities, and Applications
      1. 10.1 GENERAL DESCRIPTION
      2. 10.2 SYSTEM ARCHITECTURE
      3. 10.3 LOOKUP STRUCTURES
      4. 10.4 COUNTERS, STATISTICS AND RATE CONTROL
      5. 10.5 TRAFFIC MANAGEMENT
      6. 10.6 STATEFUL CLASSIFICATION
      7. 10.7 MULTICAST FRAMES
      8. 10.8 DATA FLOW
      9. 10.9 SUMMARY
    3. Chapter 11: EZchip Programming
      1. 11.1 INSTRUCTION PIPELINE
      2. 11.2 WRITING NP MICROCODE
      3. 11.3 PREPROCESSOR OVERVIEW
      4. 11.4 DEVELOPING AND RUNNING NP APPLICATIONS
      5. 11.6 SUMMARY
    4. Chapter 12: Parsing
      1. 12.1 INTERNAL ENGINE DIAGRAM
      2. 12.2 TOPPARSE REGISTERS
      3. 12.3 TOPPARSE STRUCTURES
      4. 12.4 TOPPARSE INSTRUCTION SET
      5. 12.5 EXAMPLE
      6. 12.6 SUMMARY
    5. Chapter 13: Searching
      1. 13.1 INTRODUCTION
      2. 13.2 INTERNAL ENGINE DIAGRAM
      3. 13.3 TOPSEARCH I STRUCTURES
      4. 13.4 INTERFACE TO TOPPARSE (INPUT TO TOPSEARCH)
      5. 13.5 INTERFACE TO TOPRESOLVE (OUTPUT OF TOPSEARCH)
      6. 13.6 HASH TABLE LEARNING
      7. 13.7 EXAMPLE
      8. 13.8 SUMMARY
    6. Chapter 14: Resolving
      1. 14.1 INTERNAL ENGINE DIAGRAM
      2. 14.2 TOPRESOLVE REGISTERS
      3. 14.3 TOPRESOLVE STRUCTURES
      4. 14.4 TOPRESOLVE INSTRUCTION SET
      5. 14.5 EXAMPLE
      6. 14.6 SUMMARY
    7. Chapter 15: Modifying
      1. 15.1 INTRODUCTION
      2. 15.2 INTERNAL ENGINE DIAGRAM
      3. 15.3 TOPMODIFY REGISTERS
      4. 15.4 TOPMODIFY STRUCTURES
      5. 15.5 TOPMODIFY INSTRUCTION SET
      6. 15.6 EXAMPLE
      7. 15.7 SUMMARY
    8. Chapter 16: Running the Virtual Local Area Network Example
      1. 16.1 INSTALLATION
      2. 16.2 GETTING STARTED
      3. 16.3 MICROCODE DEVELOPMENT WORKFLOW
      4. 16.4 SUMMARY
    9. Chapter 17: Writing Your First High-Speed Network Application
      1. 17.1 INTRODUCTION
      2. 17.2 DATA FLOW AND TOP MICROCODE
      3. 17.3 DATA STRUCTURES
      4. 17.4 SUMMARY
  13. List of Acronyms
  14. References
  15. Index