A slicable floorplan (Figure 7-8).
In the last chapter we built architectures from fairly abstract components. This chapter looks at the chip in more detail. We will assume that the block diagram is fixed; now we will study chip-level layout and circuit design. The size of the design problem requires us to develop different methods than we used to design the layout for a single NAND gate. But the basic objectives—area, delay, power—are still the same.