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Modern VLSI Design: IP-Based Design, Fourth Edition by Wayne Wolf

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4Combinational Logic Networks

Highlights:

Layouts for logic networks.Delay through networks.Power consumption.Switch logic networks.Combinational logic testing.

A cutset through a critical timing path (Figure 4-12).

A cutset through a critical timing path (Figure 4-12).

4.1 Introduction

This chapter concentrates on the design of combinational logic functions. Building a single inverter doesn’t justify a multi-billion VLSI fabrication line. We want to build complex systems of many combinational gates. To do so, we will study basic aspects of hierarchical design and analysis, especially delay and power analysis. The knowledge gained about fabrication is important ...

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