This section briefly reviews the Verilog and VHDL hardware description languages. These are both complex languages and this section is not intended to be a complete guide by any means. Hopefully, these sections can help remind you of some basic syntactic elements of the languages.
Verilog has two forms of comments:
/* this is a multiline comment */// this is a comment
Verilog defines the value set [ 0 1 x z ] of signal values. The value x is the unknown value, ...