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Mobile 3D Graphics SoC: From Algorithm to Chip by Byeong-Gyu Nam, Ju-Ho Sohn, Jeong-Ho Woo, Hoi-Jun Yoo

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6

Real Chip Implementations

PC and console graphics hardware has been evolving rapidly from simple shading accelerator to the unified shader architecture, and mobile graphics hardware has followed that trend. However, mobile systems cannot supply unlimited power or system resources to graphics hardware, so the hardware is evolving with its own architectures for low hardware cost and low power consumption. In this chapter we will explain the design concepts and architecture of several mobile graphics hardwares. First we review the RAMP architecture developed by KAIST. We then go on to introduce commercial graphics hardwares developed by industry, looking at their key features.

6.1 KAIST RAMP Architecture

As explained in earlier chapters, rendering operations such as rasterization and texture mapping dominate the 3D graphics pipeline, and require high memory bandwidth [1]. Solving the bandwidth bottleneck with traditional approaches such as high-speed crossbars and off-chip DDR-SDRAMs can result in increased power consumption. However, the limited screen resolutions in mobile terminals (e.g., QVGA) imply that a reasonable amount of integrated memory, from a few tens of kilobytes to a few megabytes, is sufficient for graphics memories, depth buffer, frame buffer, and texture memory. In addition, by embedding all the required memory with the logic on a single die, external memory accesses are dramatically reduced, so we can develop more efficient architectures in terms of performance ...

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