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Make: FPGAs by David Romano

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Chapter 6. It’s a Small World!

Easy System-On-Chip (SoC) Designing

To many of you it may seem like a daunting task to tackle a real SoC design in an FPGA. We have seen how HDL can be used to make the design task more manageable, but there’s still a learning curve. Schematic entry provides us with a graphical design entry method, but it typically doesn’t scale well for large, complex designs. Lucky for us, there is a hybrid approach that combines the best of both worlds and simplifies the SoC design task. The method involves using a hierarchical approach that begins with schematic entry for the top level, which connects our IP blocks together, and then uses HDL at the next level down to describe the function of each IP block. You can think ...

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