Legalizing SelectionDAG
In the preceding topic, we saw how an IR is converted to SelectionDAG. The whole process didn't involve any knowledge of target architecture for which we are trying to generate code. A DAG node might be illegal for the given target architecture. For example, the X86 architecture doesn't support the sdiv instruction. Instead, it supports sdivrem instruction. This target specific information is conveyed to the SelectionDAG phase by the TargetLowering interface. Targets implement this interface to describe how LLVM IR instructions should be lowered to legal SelectionDAG operations.
In our IR case, we need to 'expand' the sdiv instruction to 'sdivrem' instruction. In the function void SelectionDAGLegalize::LegalizeOp(SDNode ...
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