Chapter 7. Optimizing the Machine Code
In this chapter, we will cover the following recipes:
- Eliminating common subexpressions from machine code
- Analyzing live intervals
- Allocating registers
- Inserting the prologue-epilogue code
- Code emission
- Tail call optimization
- Sibling call optimization
Introduction
The machine code generated so far is yet to be assigned real target architecture registers. The registers seen so far have been virtual registers, which are infinite in number. The machine code generated is in the SSA form. However, the target registers are limited in number. Hence, register allocation algorithms require a lot of heuristic calculations to allocate registers in an optimal way.
But, before register allocation, there exists opportunities for ...
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