Cache Size, Cache Hierarchy, and Compiler Development
Other improvements center around increasing the level 1 (L1) and level 2 (L2) cache on the chip and further enhancing the compilers to take advantage of the cache and to find new ways to increase parallelism. The reason the cache size makes such a difference is that the cache memory is closest to the processor. The L1 cache has the shortest delay in loading data and instructions for the processor, and therefore anything loaded or stored in L1 will help to speed up the overall performance.
L2 is the next closest memory “bucket,” and so on. Therefore, an obvious way to improve the next versions of the Intel Itanium processor family will be to increase the cache sizes. Developing the chip so ...
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