Chapter 12. Parallel Operations
Previous chapters have discussed nearly all of the nonprivileged Itanium instructions that operate on 64-bit integers or double-precision floating-point values. Those instructions comprise the fundamental set of operations that one expects of a processor design with a 64-bit datapath.
When a new architecture with a wider datapath becomes available, it takes time for the industry to take advantage of the new width. We have accorded preferential treatment to full-width instructions, which should in our view be very important in applications developed for the Itanium architecture over its lifetime.
In order to optimize special, but important, legacy circumstances, the Itanium architecture supports multiwidth load ...
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