Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

Exercises

1:	When a needed information unit cannot be found in a cache—i.e., when a cache miss occurs—the design of cache systems typically calls for some fixed number of adjacent information units to be loaded into the cache, that number of bytes (probably a power of 2) being called the cache line size. Explain why this method may lower the miss rate for an instruction cache to a greater extent than for a data cache. Decide whether a compiler should generate a modestly longer alternate instruction sequence if doing so could reduce data cache misses in a particular section of a program.
2:	Explain why truly global optimization (+O4 in Table 11-3) would usually be more associated with the operation of a linker than a compiler.
3:	Explain why the branch ...