Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

D.5. Floating-Point Registers

The Itanium architecture defines 128 floating-point registers (Fr₀–Fr₁₂₇), which are 82 bits in width and can thus accommodate expanded forms of single- or double-precision IEEE values and also signed or unsigned 64-bit integers:

Unlike the general registers, the floating-point registers do not have an associated invalidity bit; instead, there is room in the coding of the data representation for a special invalidity value called NaTVal (not a thing value). NaTVal informs the CPU hardware that the contents of the floating-point register are invalid.

Table D-4 gives the nomenclature and standardized uses of the set of ...