Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles

D.4. Branch Registers

The Itanium architecture defines eight branch registers (Br₀–Br₇), which are 64 bits in width and can thus accommodate full address pointers:

Since Itanium instructions are always fetched three at a time in 128-bit bundles, the lowest four bits of a branch register are always 0. That is, the hexadecimal value of Br_n will always print with the rightmost hex character as 0.

Table D-3 gives the nomenclature and standardized uses of the Itanium branch registers. A register is scratch if it may be freely used by a routine at any calling level (caller must save anything important). A register is preserved if a calling routine depends ...