D.1. Instruction Pointer
In the Itanium architecture, the instruction pointer (IP) serves the same function, supporting the instruction fetch cycle (Section 2.2), as the register more commonly called the program counter (PC) in other architectures. It is directly accessible to certain Itanium instructions and is 64 bits in width:
Since Itanium instructions are always fetched three at a time in 128-bit bundles, the lowest 4 bits of the IP are always 0. That is, the hexadecimal value of the IP will always print with the rightmost hex character as 0.
Most architectures have one or more “instruction registers” that hold the bit patterns of instructions ...
Get Itanium® Architecture for Programmers: Understanding 64-Bit Processors and EPIC Principles now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
