Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

9.7 FINITE-STATE MACHINE ANALYSIS

Analysis of a finite-state machine is the process of finding the function of the FSM by determining the relationships among the inputs, the outputs, and the states of the flip-flops. Recall that synthesis of a finite-state machine is the process of finding a circuit implementation that satisfies the behavior of the FSM. On the other hand, analysis is breaking the FSM apart to determine its behavior and eventually its function.

We adopt the following steps to analyze a finite-state machine.

1. Identify the inputs and outputs of the finite-state machine.
2. Determine the logic expressions of the next states and the outputs simply by reading the logic networks that interconnect the inputs and outputs of the flip- flops.
3. Determine the number of all possible states, including the don't-care states. Recall that the number of states is equal to 2^N, where N is the number of flip- flops of the FSM.
4. Determine the necessary bit size of the binary numbers required to represent the states of the FSM.
5. Decide on a state assignment and construct a state assigned table using the next- state and output logic expressions.
6. Construct a state table from the state assigned table.
7. Construct a state diagram from the state table if necessary.
8. Draw or list a sample input-output timing sequence that describes the behavior of the FSM.
9. Determine the function of the FSM.

Consider the finite-state machine logic circuit illustrated in Figure 9.29. We will attempt to find the function ...