9.1 OBJECTIVES
The objectives of the chapter are to describe:
- Synchronous sequential design
- Synthesis of a finite-state machine
- Analysis of a finite-state machine
- Flip-flop selection
- State assignment
- State optimization
- FSM VHDL programming
Get Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.