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Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL by Mohammed Ferdjallah

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4.13 PACKAGES AND COMPONENTS

4.13.1 Package Statement

Packages are intended to hold commonly used declarations such as constants, type declarations, and global subprograms. Packages can be included within the same source file as other design units (such as entities and architectures) or can be placed in a separate source file and compiled into a named library. Packages may contain the following types of objects and declarations:

  • Type and subtype declarations
  • Constant declarations
  • File and alias declarations
  • Component declarations
  • Attribute declarations
  • Functions and procedures
  • Shared variables

When items from the package are required in other design units, the use statement must be included to make the package and its contents visible for each design unit. The package is stored in a separate VHDL code. It can also be included at the end of a VHDL code, which contains the entity of the architecture of the subcircuit. In both cases the package is compiled and stored in a library, which can be accessed by employing the use statement. The entity and architecture of the subcircuit referenced in a package must be compiled and made available to the VHDL code, which uses the package reference. The VHDL compiler will use the subcircuit to synthesize the complete circuit. The example in Figure 4.28 illustrates a package declaration for a 2: 1 multiplexer circuit. Notice that the package declaration included the 2: 1 multiplexer as a component declaration, which is described in the next ...

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