Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

4.6 ASSIGNMENT STATEMENTS

In the examples above, the VHDL programs use simple assignment to describe the output logic function. The 2: 1 multiplexer described in Chapter 3 has two possible output expressions depending on the value of the signal selected. VHDL provides selected signal assignment statements, which will assign a signal from several values using a selection condition. Consider the logic circuit for a 2 : 1 multiplexer shown in Figure 4.7. The VHDL program in Figure 4.8 implements the 2: 1 multiplexer in Figure 4.7. The function of the multiplexer is described in the architecture of the code using selected signal assignment statements. The signal assignment statement selected begins with the reserved keyword with followed by the selection condition, which is in the input signal, s. The reserved keyword when selects a possible value for the select signal s. The when others (reserved keyword) is included to select the last possible value of s.