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Intel Xeon Phi Processor High Performance Programming, 2nd Edition by Avinash Sodani, James Reinders, James Jeffers

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Chapter 14

Profiling and timing

Abstract

Discusses insight based on event counters built into Knights Landing, and using those counters with the Intel® VTune Amplifier. Also discusses timing, a critical element in evaluating performance.

Keywords

MIC architecture; Xeon Phi; Microcode; Event monitoring; VTune Amplifier; Performance Application Programming Interface (PAPI); VTune; VTune Amplifier XE product; Trace Analyzer and Collector (ITAC); MPI Performance Snapshot (MPS); Vectorization intensity; VPU; Bandwidth; Memory bandwidth; MPI; Cache misses; TLB; CPI; clock_gettime; gettimeofday; Timers; Time stamp counter (TSC)

What is new with Knights Landing in this chapter?

New Event-Monitoring Registers. Most advice in line with Intel Xeon ...

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