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IBM zEnterprise EC12 Technical Guide

Book Description

The popularity of the Internet and the affordability of IT hardware and software have resulted in an explosion of applications, architectures, and platforms. Workloads have changed. Many applications, including mission-critical ones, are deployed on various platforms, and the IBM® System z® design has adapted to this change. It takes into account a wide range of factors, including compatibility and investment protection, to match the IT requirements of an enterprise.

This IBM Redbooks® publication addresses the new IBM zEnterprise® System. This system consists of the IBM zEnterprise EC12 (zEC12), an updated IBM zEnterprise Unified Resource Manager, and the IBM zEnterprise BladeCenter® Extension (zBX) Model 003.

The zEC12 is designed with improved scalability, performance, security, resiliency, availability, and virtualization. The superscalar design allows the zEC12 to deliver a record level of capacity over the prior System z servers. It is powered by 120 of the world's most powerful microprocessors. These microprocessors run at 5.5 GHz and are capable of running more than 75,000 millions of instructions per second (MIPS). The zEC12 Model HA1 is estimated to provide up to 50% more total system capacity than the IBM zEnterprise 196 (z196) Model M80.

The zBX Model 003 infrastructure works with the zEC12 to enhance System z virtualization and management. It does so through an integrated hardware platform that spans mainframe, IBM POWER7®, and IBM System x® technologies. Through the Unified Resource Manager, the zEnterprise System is managed as a single pool of resources, integrating system and workload management across the environment.

This book provides information about the zEnterprise System and its functions, features, and associated software support. Greater detail is offered in areas relevant to technical planning. It is intended for systems engineers, consultants, planners, and anyone who wants to understand the zEnterprise System functions and plan for their usage. It is not intended as an introduction to mainframes. Readers are expected to be generally familiar with existing IBM System z® technology and terminology.

Table of Contents

  1. Front cover
  2. Notices
    1. Trademarks
  3. Preface
    1. Authors
    2. Now you can become a published author, too!
    3. Comments welcome
    4. Stay connected to IBM Redbooks
  4. Chapter 1. Introducing the IBM zEnterprise EC12
    1. 1.1 zEC12 highlights
      1. 1.1.1 Processor and memory
      2. 1.1.2 Capacity and performance
      3. 1.1.3 I/O subsystem and I/O features
      4. 1.1.4 Virtualization
      5. 1.1.5 Increased flexibility with z/VM mode logical partition
      6. 1.1.6 zAware mode logical partition
      7. 1.1.7 IBM System z Advanced Workload Analysis Reporter
      8. 1.1.8 Flash Express
      9. 1.1.9 10GbE RoCE Express
      10. 1.1.10 zEDC Express
      11. 1.1.11 IBM Mobile Systems Remote
      12. 1.1.12 Reliability, availability, and serviceability
    2. 1.2 zEC12 technical overview
      1. 1.2.1 Models
      2. 1.2.2 Model upgrade paths
      3. 1.2.3 Frames
      4. 1.2.4 Processor cage
      5. 1.2.5 I/O connectivity: PCIe and InfiniBand
      6. 1.2.6 I/O subsystems
      7. 1.2.7 Coupling and Server Time Protocol connectivity
      8. 1.2.8 Special purpose features
      9. 1.2.9 Reliability, availability, and serviceability
    3. 1.3 Hardware Management Consoles and Support Elements
    4. 1.4 IBM zEnterprise BladeCenter Extension (zBX) Model 003
      1. 1.4.1 Blades
      2. 1.4.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    5. 1.5 Unified Resource Manager
    6. 1.6 Operating systems and software
      1. 1.6.1 Supported operating systems
      2. 1.6.2 IBM compilers
  5. Chapter 2. Central processor complex hardware components
    1. 2.1 Frames and cage
      1. 2.1.1 A frame
      2. 2.1.2 Z frame
      3. 2.1.3 I/O cage, I/O drawer, and PCIe I/O drawer features
      4. 2.1.4 Top exit I/O cabling
    2. 2.2 Book concept
      1. 2.2.1 Book interconnect topology
      2. 2.2.2 Dual external clock facility (ECF)
      3. 2.2.3 Oscillator
      4. 2.2.4 System control
      5. 2.2.5 Book power
    3. 2.3 Multiple chip module (MCM)
    4. 2.4 Processor unit (PU) and storage control (SC) chips
      1. 2.4.1 PU chip
      2. 2.4.2 Processor unit (core)
      3. 2.4.3 PU characterization
      4. 2.4.4 Storage control (SC) chip
      5. 2.4.5 Cache level structure
    5. 2.5 Memory
      1. 2.5.1 Memory subsystem topology
      2. 2.5.2 Redundant array of independent memory (RAIM)
      3. 2.5.3 Memory configurations
      4. 2.5.4 Memory upgrades
      5. 2.5.5 Book replacement and memory
      6. 2.5.6 Flexible Memory Option
      7. 2.5.7 Pre-planned memory
    6. 2.6 Reliability, availability, and serviceability (RAS)
      1. 2.6.1 RAS in the CPC memory subsystem
      2. 2.6.2 General zEC12 RAS features
    7. 2.7 Connectivity
      1. 2.7.1 Redundant I/O interconnect
      2. 2.7.2 Enhanced book availability
      3. 2.7.3 Book upgrade
    8. 2.8 Model configurations
      1. 2.8.1 Upgrades
      2. 2.8.2 Concurrent PU conversions
      3. 2.8.3 Model capacity identifier
      4. 2.8.4 Model capacity identifier and MSU value
      5. 2.8.5 Capacity Backup
      6. 2.8.6 On/Off Capacity on Demand and CPs
    9. 2.9 Power and cooling
      1. 2.9.1 Power consumption
      2. 2.9.2 High voltage DC power
      3. 2.9.3 Internal Battery Feature (IBF)
      4. 2.9.4 Power capping and power saving
      5. 2.9.5 Power estimation tool
      6. 2.9.6 Cooling
      7. 2.9.7 Radiator Unit
      8. 2.9.8 Water Cooling Unit (WCU)
      9. 2.9.9 Backup air cooling system
    10. 2.10 Summary of zEC12 structure
  6. Chapter 3. Central processor complex system design
    1. 3.1 Overview
    2. 3.2 Design highlights
    3. 3.3 Book design
      1. 3.3.1 Cache levels and memory structure
      2. 3.3.2 Book interconnect topology
    4. 3.4 Processor unit design
      1. 3.4.1 Out-of-order (OOO) execution
      2. 3.4.2 Superscalar processor
      3. 3.4.3 Compression and cryptography accelerators on a chip
      4. 3.4.4 Decimal floating point (DFP) accelerator
      5. 3.4.5 IEEE floating point
      6. 3.4.6 Processor error detection and recovery
      7. 3.4.7 Branch prediction
      8. 3.4.8 Wild branch
      9. 3.4.9 Translation lookaside buffer (TLB)
      10. 3.4.10 Instruction fetching, decoding, and grouping
      11. 3.4.11 Extended Translation Facility
      12. 3.4.12 Instruction set extensions
      13. 3.4.13 Transactional execution (TX)
      14. 3.4.14 Runtime instrumentation (RI)
    5. 3.5 Processor unit functions
      1. 3.5.1 Overview
      2. 3.5.2 Central processors
      3. 3.5.3 Integrated Facility for Linux
      4. 3.5.4 Internal Coupling Facility
      5. 3.5.5 System z Application Assist Processors (zAAPs)
      6. 3.5.6 System z Integrated Information Processor (zIIP)
      7. 3.5.7 zAAP on zIIP capability
      8. 3.5.8 System assist processors (SAPs)
      9. 3.5.9 Reserved processors
      10. 3.5.10 Integrated firmware processor
      11. 3.5.11 Processor unit assignment
      12. 3.5.12 Sparing rules
      13. 3.5.13 Increased flexibility with z/VM mode partitions
    6. 3.6 Memory design
      1. 3.6.1 Overview
      2. 3.6.2 Central storage (CS)
      3. 3.6.3 Expanded storage
      4. 3.6.4 Hardware system area (HSA)
    7. 3.7 Logical partitioning
      1. 3.7.1 Overview
      2. 3.7.2 Storage operations
      3. 3.7.3 Reserved storage
      4. 3.7.4 Logical partition storage granularity
      5. 3.7.5 LPAR dynamic storage reconfiguration (DSR)
    8. 3.8 Intelligent Resource Director (IRD)
    9. 3.9 Clustering technology
      1. 3.9.1 Coupling facility control code (CFCC)
      2. 3.9.2 Dynamic CF dispatching
  7. Chapter 4. Central processor complex I/O system structure
    1. 4.1 Introduction to InfiniBand and PCIe
      1. 4.1.1 InfiniBand specification
      2. 4.1.2 Data, signaling, and link rates
      3. 4.1.3 PCIe
    2. 4.2 I/O system overview
      1. 4.2.1 Characteristics
      2. 4.2.2 Summary of supported I/O features
    3. 4.3 I/O cages
    4. 4.4 I/O drawers
    5. 4.5 PCIe I/O drawers
    6. 4.6 I/O cage, I/O drawer, and PCIe I/O drawer offerings
    7. 4.7 Fanouts
      1. 4.7.1 HCA2-C fanout (FC 0162)
      2. 4.7.2 PCIe copper fanout (FC 0169)
      3. 4.7.3 HCA2-O (12x IFB) fanout (FC 0163)
      4. 4.7.4 HCA2-O LR (1x IFB) fanout (FC 0168)
      5. 4.7.5 HCA3-O (12x IFB) fanout (FC 0171)
      6. 4.7.6 HCA3-O LR (1x IFB) fanout (FC 0170)
      7. 4.7.7 Fanout considerations
      8. 4.7.8 Fanout summary
    8. 4.8 I/O feature cards
      1. 4.8.1 I/O feature card ordering information
      2. 4.8.2 PCHID report
    9. 4.9 Connectivity
      1. 4.9.1 I/O feature support and configuration rules
      2. 4.9.2 IBM ESCON channels
      3. 4.9.3 FICON channels
      4. 4.9.4 OSA-Express5S
      5. 4.9.5 OSA-Express4S features
      6. 4.9.6 OSA-Express3 features
      7. 4.9.7 OSA-Express for ensemble connectivity
      8. 4.9.8 HiperSockets
    10. 4.10 Parallel Sysplex connectivity
      1. 4.10.1 Coupling links
      2. 4.10.2 External clock facility
    11. 4.11 Cryptographic functions
      1. 4.11.1 CPACF functions (FC 3863)
      2. 4.11.2 Crypto Express4S feature (FC 0865)
      3. 4.11.3 Crypto Express3 feature (FC 0864)
    12. 4.12 Integrated firmware processor
    13. 4.13 Flash Express
    14. 4.14 10 GbE RoCE Express
    15. 4.15 zEDC Express
  8. Chapter 5. Central processor complex channel subsystem
    1. 5.1 Channel subsystem
      1. 5.1.1 Multiple channel subsystems concept
      2. 5.1.2 CSS elements
      3. 5.1.3 Multiple subchannel sets
      4. 5.1.4 Parallel access volumes and extended address volumes
      5. 5.1.5 Logical partition name and identification
      6. 5.1.6 Physical channel ID
      7. 5.1.7 Channel spanning
      8. 5.1.8 Multiple CSS construct
      9. 5.1.9 Adapter ID (AID)
      10. 5.1.10 Channel subsystem enhancement for I/O resilience
    2. 5.2 I/O configuration management
    3. 5.3 Channel subsystem summary
    4. 5.4 System-initiated CHPID reconfiguration
    5. 5.5 Multipath initial program load (IPL)
  9. Chapter 6. Cryptography
    1. 6.1 Cryptographic synchronous functions
    2. 6.2 Cryptographic asynchronous functions
      1. 6.2.1 Secure key functions
      2. 6.2.2 Additional functions
    3. 6.3 CPACF protected key
    4. 6.4 PKCS #11 overview
      1. 6.4.1 PKCS #11 model
      2. 6.4.2 z/OS PKCS #11 implementation
      3. 6.4.3 Secure IBM Enterprise PKCS #11 (EP11) Coprocessor
    5. 6.5 Cryptographic feature codes
    6. 6.6 CP Assist for Cryptographic Function (CPACF)
    7. 6.7 Crypto Express4S
    8. 6.8 Crypto Express3
    9. 6.9 Tasks that are run by PCIe Crypto Express
      1. 6.9.1 PCIe Crypto Express as a CCA coprocessor
      2. 6.9.2 PCIe Crypto Express as an EP11 coprocessor
      3. 6.9.3 PCIe Crypto Express as an accelerator
      4. 6.9.4 IBM Common Cryptographic Architecture (CCA) Enhancements
    10. 6.10 TKE workstation feature
      1. 6.10.1 TKE 7.0 Licensed Internal Code (LIC)
      2. 6.10.2 TKE 7.1 Licensed Internal Code (LIC)
      3. 6.10.3 TKE 7.2 Licensed Internal Code (LIC)
      4. 6.10.4 Logical partition, TKE host, and TKE target
      5. 6.10.5 Optional smart card reader
    11. 6.11 Cryptographic functions comparison
    12. 6.12 Software support
  10. Chapter 7. zEnterprise BladeCenter Extension (zBX) Model 003
    1. 7.1 zBX concepts
    2. 7.2 zBX hardware description
      1. 7.2.1 zBX racks
      2. 7.2.2 Top of Rack (ToR) switches
      3. 7.2.3 zBX BladeCenter chassis
      4. 7.2.4 zBX blades
      5. 7.2.5 Power distribution unit (PDU)
    3. 7.3 zBX entitlements, firmware, and upgrades
      1. 7.3.1 zBX management
      2. 7.3.2 zBX firmware
    4. 7.4 zBX connectivity
      1. 7.4.1 Intranode management network (INMN)
      2. 7.4.2 Primary and alternate HMCs
      3. 7.4.3 Intraensemble data network (IEDN)
      4. 7.4.4 Network connectivity rules with zBX
      5. 7.4.5 Network security considerations with zBX
      6. 7.4.6 zBX storage connectivity
    5. 7.5 zBX connectivity examples
      1. 7.5.1 Single-node ensemble with a zBX
      2. 7.5.2 Dual-node ensemble with a single zBX
      3. 7.5.3 Dual-node ensemble with two zBXs
    6. 7.6 References
  11. Chapter 8. Software support
    1. 8.1 Operating systems summary
    2. 8.2 Support by operating system
      1. 8.2.1 z/OS
      2. 8.2.2 z/VM
      3. 8.2.3 z/VSE
      4. 8.2.4 z/TPF
      5. 8.2.5 Linux on System z
      6. 8.2.6 zEC12 function support summary
    3. 8.3 Support by function
      1. 8.3.1 Single system image
      2. 8.3.2 zAAP support
      3. 8.3.3 zIIP support
      4. 8.3.4 zAAP on zIIP capability
      5. 8.3.5 Transactional Execution (TX)
      6. 8.3.6 Maximum main storage size
      7. 8.3.7 Flash Express
      8. 8.3.8 zEnterprise Data Compression (zEDC) Express
      9. 8.3.9 10GbE RoCE Express
      10. 8.3.10 Large page support
      11. 8.3.11 Guest support for execute-extensions facility
      12. 8.3.12 Hardware decimal floating point
      13. 8.3.13 Up to 60 logical partitions
      14. 8.3.14 Separate LPAR management of PUs
      15. 8.3.15 Dynamic LPAR memory upgrade
      16. 8.3.16 LPAR physical capacity limit enforcement
      17. 8.3.17 Capacity Provisioning Manager
      18. 8.3.18 Dynamic PU add
      19. 8.3.19 HiperDispatch
      20. 8.3.20 The 63.75-K subchannels
      21. 8.3.21 Multiple subchannel sets
      22. 8.3.22 Third subchannel set
      23. 8.3.23 IPL from an alternate subchannel set
      24. 8.3.24 MIDAW facility
      25. 8.3.25 HiperSockets Completion Queue
      26. 8.3.26 HiperSockets integration with the intraensemble data network (IEDN)
      27. 8.3.27 HiperSockets Virtual Switch Bridge
      28. 8.3.28 HiperSockets Multiple Write Facility
      29. 8.3.29 HiperSockets IPv6
      30. 8.3.30 HiperSockets Layer 2 support
      31. 8.3.31 HiperSockets network traffic analyzer for Linux on System z
      32. 8.3.32 FICON Express8S
      33. 8.3.33 FICON Express8
      34. 8.3.34 z/OS discovery and autoconfiguration (zDAC)
      35. 8.3.35 High performance FICON (zHPF)
      36. 8.3.36 Request node identification data
      37. 8.3.37 24k subchannels for the FICON Express
      38. 8.3.38 Extended distance FICON
      39. 8.3.39 Platform and name server registration in FICON channel
      40. 8.3.40 FICON link incident reporting
      41. 8.3.41 FCP provides increased performance
      42. 8.3.42 N-Port ID virtualization (NPIV)
      43. 8.3.43 OSA-Express5S 10-Gigabit Ethernet LR and SR
      44. 8.3.44 OSA-Express5S Gigabit Ethernet LX and SX
      45. 8.3.45 OSA-Express5S 1000BASE-T Ethernet
      46. 8.3.46 OSA-Express4S 10-Gigabit Ethernet LR and SR
      47. 8.3.47 OSA-Express4S Gigabit Ethernet LX and SX
      48. 8.3.48 OSA-Express4S 1000BASE-T Ethernet
      49. 8.3.49 OSA-Express3 10-Gigabit Ethernet LR and SR
      50. 8.3.50 OSA-Express3 Gigabit Ethernet LX and SX
      51. 8.3.51 OSA-Express3 1000BASE-T Ethernet
      52. 8.3.52 Open Systems Adapter for IBM zAware
      53. 8.3.53 Open Systems Adapter for Ensemble
      54. 8.3.54 Intranode management network (INMN)
      55. 8.3.55 Intraensemble data network (IEDN)
      56. 8.3.56 OSA-Express5S and OSA-Express4S NCP support (OSN)
      57. 8.3.57 Integrated Console Controller
      58. 8.3.58 VLAN management enhancements
      59. 8.3.59 GARP VLAN Registration Protocol
      60. 8.3.60 Inbound workload queuing (IWQ) for OSA-Express5S, OSA-Express4S, and OSA-Express3
      61. 8.3.61 Inbound workload queuing (IWQ) for Enterprise Extender
      62. 8.3.62 Query and display OSA configuration
      63. 8.3.63 Link aggregation support for z/VM
      64. 8.3.64 QDIO data connection isolation for z/VM
      65. 8.3.65 QDIO interface isolation for z/OS
      66. 8.3.66 QDIO optimized latency mode (OLM)
      67. 8.3.67 Large send for IPv6 packets
      68. 8.3.68 OSA-Express5S and OSA-Express4S checksum offload
      69. 8.3.69 Checksum offload for IPv4 packets when in QDIO mode
      70. 8.3.70 Adapter interruptions for QDIO
      71. 8.3.71 OSA Dynamic LAN idle
      72. 8.3.72 OSA Layer 3 virtual MAC for z/OS environments
      73. 8.3.73 QDIO Diagnostic Synchronization
      74. 8.3.74 Network Traffic Analyzer
      75. 8.3.75 Program directed re-IPL
      76. 8.3.76 Coupling over InfiniBand
      77. 8.3.77 Dynamic I/O support for InfiniBand CHPIDs
    4. 8.4 Cryptographic support
      1. 8.4.1 CP Assist for Cryptographic Function (CPACF)
      2. 8.4.2 Crypto Express4S
      3. 8.4.3 Crypto Express3
      4. 8.4.4 Web deliverables
      5. 8.4.5 z/OS ICSF FMIDs
      6. 8.4.6 ICSF migration considerations
    5. 8.5 z/OS migration considerations
      1. 8.5.1 General guidelines
      2. 8.5.2 Hardware Configuration Definition (HCD)
      3. 8.5.3 InfiniBand coupling links
      4. 8.5.4 Large page support
      5. 8.5.5 HiperDispatch
      6. 8.5.6 Capacity Provisioning Manager
      7. 8.5.7 Decimal floating point and z/OS XL C/C++ considerations
      8. 8.5.8 IBM System z Advanced Workload Analysis Reporter (IBM zAware)
    6. 8.6 Coupling facility and CFCC considerations
    7. 8.7 MIDAW facility
      1. 8.7.1 MIDAW technical description
      2. 8.7.2 Extended format data sets
      3. 8.7.3 Performance benefits
    8. 8.8 IOCP
    9. 8.9 Worldwide port name (WWPN) tool
    10. 8.10 ICKDSF
    11. 8.11 zEnterprise BladeCenter Extension (zBX) Model 003 software support
      1. 8.11.1 IBM blades
      2. 8.11.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    12. 8.12 Software licensing considerations
      1. 8.12.1 MLC pricing metrics
      2. 8.12.2 Advanced Workload License Charges (AWLC)
      3. 8.12.3 System z new application license charges (zNALC)
      4. 8.12.4 Select application license charges (SALC)
      5. 8.12.5 Midrange Workload License Charges (MWLC)
      6. 8.12.6 Parallel Sysplex License Charges (PSLC)
      7. 8.12.7 System z International Program License Agreement (IPLA)
    13. 8.13 References
  12. Chapter 9. System upgrades
    1. 9.1 Upgrade types
      1. 9.1.1 Overview of upgrade types
      2. 9.1.2 Terminology related to CoD for zEC12 systems
      3. 9.1.3 Permanent upgrades
      4. 9.1.4 Temporary upgrades
    2. 9.2 Concurrent upgrades
      1. 9.2.1 Model upgrades
      2. 9.2.2 Customer Initiated Upgrade (CIU) facility
      3. 9.2.3 Summary of concurrent upgrade functions
    3. 9.3 Miscellaneous equipment specification (MES) upgrades
      1. 9.3.1 MES upgrade for processors
      2. 9.3.2 MES upgrades for memory
      3. 9.3.3 MES upgrades for I/O
      4. 9.3.4 MES upgrades for the zBX
      5. 9.3.5 Summary of plan-ahead features
    4. 9.4 Permanent upgrade through the CIU facility
      1. 9.4.1 Ordering
      2. 9.4.2 Retrieval and activation
    5. 9.5 On/Off Capacity on Demand
      1. 9.5.1 Overview
      2. 9.5.2 Ordering
      3. 9.5.3 On/Off CoD testing
      4. 9.5.4 Activation and deactivation
      5. 9.5.5 Termination
      6. 9.5.6 z/OS capacity provisioning
    6. 9.6 Capacity for Planned Event (CPE)
    7. 9.7 Capacity Backup (CBU)
      1. 9.7.1 Ordering
      2. 9.7.2 CBU activation and deactivation
      3. 9.7.3 Automatic CBU enablement for GDPS
    8. 9.8 Nondisruptive upgrades
      1. 9.8.1 Components
      2. 9.8.2 Concurrent upgrade considerations
    9. 9.9 Summary of Capacity on Demand offerings
    10. 9.10 Reference
  13. Chapter 10. Reliability, availability, and serviceability
    1. 10.1 zEC12 availability characteristics
    2. 10.2 zEC12 RAS functions
      1. 10.2.1 Scheduled outages
      2. 10.2.2 Unscheduled outages
    3. 10.3 zEC12 enhanced book availability (EBA)
      1. 10.3.1 EBA planning considerations
      2. 10.3.2 Enhanced book availability processing
    4. 10.4 zEC12 enhanced driver maintenance (EDM)
    5. 10.5 RAS capability for the HMC and SE
    6. 10.6 RAS capability for zBX
    7. 10.7 Considerations for PowerHA in zBX environment
    8. 10.8 IBM System z Advanced Workload Analysis Reporter (IBM zAware)
    9. 10.9 RAS capability for Flash Express
  14. Chapter 11. Environmental requirements
    1. 11.1 zEC12 power and cooling
      1. 11.1.1 Power consumption
      2. 11.1.2 Internal Battery Feature
      3. 11.1.3 Emergency power-off switch
      4. 11.1.4 Cooling requirements
    2. 11.2 IBM zEnterprise EC12 physical specifications
    3. 11.3 IBM zEnterprise EC12 physical planning
      1. 11.3.1 Raised floor or non-raised floor
      2. 11.3.2 Top Exit Power feature
      3. 11.3.3 Top Exit I/O Cabling feature
      4. 11.3.4 Weight distribution plate
      5. 11.3.5 Three-in-one bolt-down kit for raised floor
    4. 11.4 zBX environmental requirements
      1. 11.4.1 zBX configurations
      2. 11.4.2 zBX power components
      3. 11.4.3 zBX cooling
      4. 11.4.4 zBX physical specifications
    5. 11.5 Energy management
      1. 11.5.1 Power estimation tool
      2. 11.5.2 Query maximum potential power
      3. 11.5.3 System Activity Display and Monitors Dashboard
      4. 11.5.4 IBM Systems Director Active Energy Manager
      5. 11.5.5 Unified Resource Manager: Energy management
  15. Chapter 12. Hardware Management Console and Support Element
    1. 12.1 Introduction to the HMC and SE
    2. 12.2 SE driver support with the new HMC
      1. 12.2.1 HMC Feature Code  0092 changes
    3. 12.3 HMC and SE enhancements and changes
      1. 12.3.1 HMC media support
      2. 12.3.2 Tree Style User Interface and Classic Style User Interface
    4. 12.4 HMC and SE connectivity
      1. 12.4.1 Hardware prerequisite changes
      2. 12.4.2 TCP/IP Version 6 on the HMC and SE
      3. 12.4.3 Assigning addresses to the HMC and SE
    5. 12.5 Remote Support Facility (RSF)
      1. 12.5.1 Security characteristics
      2. 12.5.2 RSF connections to IBM and the Enhanced IBM Service Support System
      3. 12.5.3 HMC and SE remote operations
    6. 12.6 HMC and SE key capabilities
      1. 12.6.1 Central processor complex (CPC) management
      2. 12.6.2 Logical partition management
      3. 12.6.3 Operating system communication
      4. 12.6.4 HMC and SE microcode
      5. 12.6.5 Monitoring
      6. 12.6.6 IBM Mobile Systems Remote
      7. 12.6.7 Capacity on Demand (CoD) support
      8. 12.6.8 Feature on Demand (FoD) support
      9. 12.6.9 Server Time Protocol support
      10. 12.6.10 NTP client and server support on the HMC
      11. 12.6.11 Security and user ID management
      12. 12.6.12 System Input/Output Configuration Analyzer on the SE and HMC
      13. 12.6.13 Automated operations
      14. 12.6.14 Cryptographic support
      15. 12.6.15 z/VM virtual machine management
      16. 12.6.16 Installation support for z/VM using the HMC
    7. 12.7 HMC in an ensemble
      1. 12.7.1 Unified Resource Manager
      2. 12.7.2 Ensemble definition and management
      3. 12.7.3 HMC availability
      4. 12.7.4 Considerations for multiple HMCs
      5. 12.7.5 HMC browser session to a primary HMC
      6. 12.7.6 HMC ensemble topology
  16. Chapter 13. Performance
    1. 13.1 LSPR workload suite
    2. 13.2 Fundamental components of workload capacity performance
    3. 13.3 Relative nest intensity
    4. 13.4 LSPR workload categories based on relative nest intensity
    5. 13.5 Relating production workloads to LSPR workloads
    6. 13.6 Workload performance variation
  17. Appendix A. IBM System z Advanced Workload Analysis Reporter (IBM zAware)
    1. A.1 Troubleshooting in complex IT environments
    2. A.2 Introducing IBM zAware
    3. A.3 Understanding IBM zAware technology
    4. A.4 Learning IBM zAware prerequisites
    5. A.5 Configuring and using IBM zAware virtual appliance
  18. Appendix B. Channel options
  19. Appendix C. Flash Express
    1. C.1 Flash Express overview
    2. C.2 Using Flash Express
    3. C.3 Security on Flash Express
  20. Appendix D. Remote Direct Memory Access over Converged Ethernet (RoCE)
    1. D.1 Overview
    2. D.2 Hardware
    3. D.3 Software exploitation
  21. Appendix E. zEnterprise Data Compression (zEDC) Express
    1. E.1 Overview
    2. E.2 zEDC Express
    3. E.3 Software support
  22. Appendix F. Native Peripheral Component Interconnect Express (PCIe)
    1. F.1 Design of native PCIe I/O adapter management
    2. F.2 Native PCIe adapter
    3. F.3 Integrated firmware processor (IFP)
    4. F.4 Resource Groups (RGs)
    5. F.5 Native PCIe feature plugging rules
    6. F.6 Management tasks
    7. F.7 zEDC Express
    8. F.8 10GbE RoCE Express
    9. F.9 Native PCIe feature definitions
  23. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. Help from IBM
  24. Back cover