IBM zEnterprise BC12 Technical Guide

IBM zEnterprise BC12 Technical Guide

by Octavian Lascu, Hua Bin Chu, Ivan Dobos, Luiz Fadel, Wolfgang Fries, Parwez Hamid, Fernando E Nogal, Frank Packheiser, Ewerson Palacio, Martijn Raave, Vicente Ranieri Jr., Andre Spahni, Chen Zhu
Released February 2014
Publisher(s): IBM Redbooks
ISBN: None

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Book description

The popularity of the Internet and the affordability of information technology (IT) hardware and software have resulted in an explosion dramatic increase in the number of applications, architectures, and platforms. Workloads have changed. Many applications, including mission-critical ones, are deployed on a variety of platforms, and the IBM® System z® design has adapted to this change. It takes into account a wide range of factors, including compatibility and investment protection, to match the IT requirements of an enterprise.

This IBM Redbooks® publication provides information about the IBM zEnterprise® BC12 (zBC12), an IBM scalable mainframe server. IBM is taking a revolutionary approach by integrating separate platforms under the well-proven System z hardware management capabilities, while extending System z qualities of service to those platforms.

The zEnterprise System consists of the zBC12 central processor complex, the IBM zEnterprise Unified Resource Manager, and the IBM zEnterprise BladeCenter® Extension (zBX). The zBC12 is designed with improved scalability, performance, security, resiliency, availability, and virtualization. The zBC12 provides the following improvements over its predecessor, the IBM zEnterprise 114 (z114):

  • Up to a 36% performance boost per core running at 4.2 GHz

  • Up to 58% more capacity for traditional workloads

  • Up to 62% more capacity for Linux workloads


    • The zBX infrastructure works with the zBC12 to enhance System z virtualization and management through an integrated hardware platform that spans mainframe, IBM POWER7®, and IBM System x® technologies. The federated capacity from multiple architectures of the zEnterprise System is managed as a single pool of resources, integrating system and workload management across the environment through the Unified Resource Manager.

    This book provides an overview of the zBC12 and its functions, features, and associated software support. Greater detail is offered in areas relevant to technical planning. This book is intended for systems engineers, consultants, planners, and anyone who wants to understand zEnterprise System functions and plan for their usage. It is not intended as an introduction to mainframes. Readers are expected to be generally familiar with existing IBM System z technology and terminology.

    Table of contents

    1. Front cover
    2. Notices
      1. Trademarks
    3. Preface
      1. Authors
      2. Now you can become a published author, too!
      3. Comments welcome
      4. Stay connected to IBM Redbooks publications
    4. Chapter 1. Introducing the IBM zEnterprise BC12
      1. 1.1 Highlights of the zBC12
        1. 1.1.1 Processor and memory
        2. 1.1.2 Capacity and performance
        3. 1.1.3 I/O subsystem and I/O features
        4. 1.1.4 Virtualization
        5. 1.1.5 Increased flexibility with z/VM-mode partitions
        6. 1.1.6 IBM System z Advanced Workload Analysis Reporter
        7. 1.1.7 The zAware mode logical partition
        8. 1.1.8 Flash Express
        9. 1.1.9 10GbE RoCE Express
        10. 1.1.10 IBM zEnterprise Data Compression Express
        11. 1.1.11 IBM Mobile Systems Remote
        12. 1.1.12 Reliability, availability, and serviceability
      2. 1.2 A technical overview of zBC12
        1. 1.2.1 Models
        2. 1.2.2 Model upgrade paths
        3. 1.2.3 Frame
        4. 1.2.4 Processor drawer
        5. 1.2.5 I/O connectivity: PCIe and InfiniBand
        6. 1.2.6 I/O subsystems
        7. 1.2.7 Coupling and Server Time Protocol connectivity
        8. 1.2.8 Special-purpose features
        9. 1.2.9 Reliability, availability, and serviceability
      3. 1.3 Hardware Management Consoles and Support Elements
      4. 1.4 IBM zEnterprise BladeCenter Extension Model 003
        1. 1.4.1 Blades
        2. 1.4.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
      5. 1.5 Unified Resource Manager
      6. 1.6 Operating systems and software
        1. 1.6.1 Supported operating systems
        2. 1.6.2 IBM compilers
    5. Chapter 2. Central processor complex hardware components
      1. 2.1 Frames and drawers
        1. 2.1.1 The zBC12 frame
        2. 2.1.2 PCIe I/O drawer and I/O drawer features
      2. 2.2 Processor drawer concept
        1. 2.2.1 Processor drawer interconnect topology
        2. 2.2.2 Oscillator
        3. 2.2.3 Pulse per second
        4. 2.2.4 System control
        5. 2.2.5 Processor drawer power
      3. 2.3 Single-chip module
      4. 2.4 Processor units and storage control chips
        1. 2.4.1 Processor unit chip
        2. 2.4.2 Processor unit (core)
        3. 2.4.3 Processor unit characterization
        4. 2.4.4 Storage control chip
        5. 2.4.5 Cache levels structure
      5. 2.5 Memory
        1. 2.5.1 Memory subsystem topology
        2. 2.5.2 Redundant array of independent memory
        3. 2.5.3 Memory configurations
        4. 2.5.4 Memory upgrades
        5. 2.5.5 Preplanned memory
      6. 2.6 Reliability, availability, and serviceability
      7. 2.7 Connectivity
        1. 2.7.1 Redundant I/O interconnect
      8. 2.8 Model configurations
        1. 2.8.1 Upgrades
        2. 2.8.2 Concurrent PU conversions
        3. 2.8.3 Model capacity identifier
        4. 2.8.4 Model capacity identifier and MSU values
        5. 2.8.5 Capacity BackUp
        6. 2.8.6 On/Off Capacity on Demand and CPs
      9. 2.9 Power and cooling
        1. 2.9.1 Power considerations
        2. 2.9.2 High-voltage DC power
        3. 2.9.3 Internal Battery Feature
        4. 2.9.4 Power capping
        5. 2.9.5 Power estimation tool
        6. 2.9.6 Cooling requirements
      10. 2.10 Summary of zBC12 structure
    6. Chapter 3. Central processor complex system design
      1. 3.1 Overview
      2. 3.2 Design highlights
      3. 3.3 Processor drawer design
        1. 3.3.1 Cache levels and memory structure
        2. 3.3.2 Processor drawer interconnect topology
      4. 3.4 Processor unit design
        1. 3.4.1 Out-of-order execution
        2. 3.4.2 Superscalar processor
        3. 3.4.3 Compression and cryptography accelerators on a chip
        4. 3.4.4 Decimal floating point accelerator
        5. 3.4.5 IEEE floating point
        6. 3.4.6 Processor error detection and recovery
        7. 3.4.7 Branch prediction
        8. 3.4.8 .Wild branch
        9. 3.4.9 Translation lookaside buffer
        10. 3.4.10 Instruction fetching, decoding, and grouping
        11. 3.4.11 Extended translation facility
        12. 3.4.12 Instruction set extensions
        13. 3.4.13 Transactional execution
        14. 3.4.14 Runtime instrumentation
      5. 3.5 Processor unit functions
        1. 3.5.1 Overview
        2. 3.5.2 Central processors
        3. 3.5.3 Integrated Facility for Linux
        4. 3.5.4 Internal coupling facilities
        5. 3.5.5 System z Application Assist Processors
        6. 3.5.6 System z Integrated Information Processor
        7. 3.5.7 The zAAP on zIIP capability
        8. 3.5.8 System Assist Processors
        9. 3.5.9 Reserved processors
        10. 3.5.10 Integrated firmware processor
        11. 3.5.11 Processor unit assignment
        12. 3.5.12 Sparing rules
        13. 3.5.13 Increased flexibility with z/VM-mode partitions
      6. 3.6 Memory design
        1. 3.6.1 Overview
        2. 3.6.2 Central storage
        3. 3.6.3 Expanded storage
        4. 3.6.4 Hardware system area
      7. 3.7 Logical partitioning
        1. 3.7.1 Overview
        2. 3.7.2 Storage operations
        3. 3.7.3 Reserved storage
        4. 3.7.4 Logical partition storage granularity
        5. 3.7.5 LPAR dynamic storage reconfiguration
      8. 3.8 Intelligent resource director
      9. 3.9 Clustering technology
        1. 3.9.1 Coupling facility control code
        2. 3.9.2 Dynamic CF dispatching
    7. Chapter 4. Central processor complex I/O system structure
      1. 4.1 Introduction to InfiniBand and PCIe
        1. 4.1.1 InfiniBand specification
        2. 4.1.2 Data, signaling, and link rates
        3. 4.1.3 PCIe
      2. 4.2 I/O system overview
        1. 4.2.1 Characteristics
        2. 4.2.2 Summary of supported I/O features
      3. 4.3 I/O drawers
      4. 4.4 PCIe I/O drawers
      5. 4.5 I/O drawer and PCIe I/O drawer offerings
      6. 4.6 Fanouts
        1. 4.6.1 HCA2-C fanout (FC 0162)
        2. 4.6.2 PCIe copper fanout (FC 0169)
        3. 4.6.3 HCA2-O (12xIFB) fanout (FC 0163)
        4. 4.6.4 HCA2-O LR (1xIFB) fanout (FC 0168)
        5. 4.6.5 HCA3-O (12xIFB) fanout (FC 0171)
        6. 4.6.6 HCA3-O LR (1xIFB) fanout (FC 0170)
        7. 4.6.7 Fanout considerations
        8. 4.6.8 Fanout summary
      7. 4.7 I/O feature cards
        1. 4.7.1 I/O feature card types ordering information
        2. 4.7.2 PCHID report
      8. 4.8 Connectivity
        1. 4.8.1 Feature support and configuration rules
        2. 4.8.2 Enterprise Systems Connection channels
        3. 4.8.3 FICON channels
        4. 4.8.4 OSA-Express5S
        5. 4.8.5 OSA-Express4S
        6. 4.8.6 OSA-Express3
        7. 4.8.7 OSA-Express for ensemble connectivity
        8. 4.8.8 HiperSockets
      9. 4.9 Parallel Sysplex connectivity
        1. 4.9.1 Coupling links
        2. 4.9.2 Oscillator card
      10. 4.10 Cryptographic functions
        1. 4.10.1 CPACF functions (FC 3863)
        2. 4.10.2 Crypto Express4S feature (FC 0865)
        3. 4.10.3 Crypto Express3 feature (FC 0864)
        4. 4.10.4 Crypto Express3-1P feature (FC 0871)
      11. 4.11 Integrated firmware processor
      12. 4.12 Flash Express
      13. 4.13 10GbE RoCE Express
      14. 4.14 The zEDC Express
    8. Chapter 5. Central processor complex channel subsystem
      1. 5.1 Channel subsystem
        1. 5.1.1 Multiple CSSs concept
        2. 5.1.2 CSS elements
        3. 5.1.3 Multiple subchannel sets
        4. 5.1.4 Parallel access volumes and extended address volumes
        5. 5.1.5 Logical partition name and identification
        6. 5.1.6 Physical channel ID
        7. 5.1.7 Channel spanning
        8. 5.1.8 Multiple CSS construct
        9. 5.1.9 Adapter ID
      2. 5.2 Input/output configuration management
      3. 5.3 Channel subsystem summary
      4. 5.4 System-initiated channel path identifier reconfiguration
      5. 5.5 Multipath initial program load (IPL)
    9. Chapter 6. Cryptography
      1. 6.1 Cryptographic synchronous functions
      2. 6.2 Cryptographic asynchronous functions
        1. 6.2.1 Secure key functions
      3. 6.3 CPACF protected key
        1. 6.3.1 Other key functions
      4. 6.4 PKCS #11 Overview
        1. 6.4.1 The PKCS #11 model
        2. 6.4.2 The z/OS PKCS #11 implementation
        3. 6.4.3 Secure IBM Enterprise PKCS #11 (EP11) coprocessor
      5. 6.5 Cryptographic feature codes
      6. 6.6 CP Assist for Cryptographic Function
      7. 6.7 Crypto Express4S
      8. 6.8 Crypto Express3
        1. 6.8.1 Crypto Express3 coprocessor
        2. 6.8.2 Crypto Express3 accelerator
        3. 6.8.3 Configuration rules
      9. 6.9 Tasks that are run by PCIe Crypto Express
        1. 6.9.1 PCIe Crypto Express as a CCA coprocessor
        2. 6.9.2 PCIe Crypto Express as an EP11 coprocessor
        3. 6.9.3 PCIe Crypto Express as an accelerator
        4. 6.9.4 IBM CCA enhancements
      10. 6.10 TKE workstation feature
        1. 6.10.1 TKE 7.0 Licensed Internal Code
        2. 6.10.2 TKE 7.1 Licensed Internal Code
        3. 6.10.3 TKE 7.2 Licensed Internal Code
        4. 6.10.4 Logical partition, TKE host, and TKE target
        5. 6.10.5 Optional smart card reader
      11. 6.11 Cryptographic functions comparison
      12. 6.12 Software support
    10. Chapter 7. IBM zEnterprise BladeCenter Extension Model 003
      1. 7.1 IBM zBX concepts
      2. 7.2 IBM zBX hardware description
        1. 7.2.1 IBM zBX racks
        2. 7.2.2 Top of rack (TOR) switches
        3. 7.2.3 IBM zBX BladeCenter chassis
        4. 7.2.4 IBM zBX blades
        5. 7.2.5 Power distribution unit
      3. 7.3 IBM zBX entitlements, firmware, and upgrades
        1. 7.3.1 IBM zBX management
        2. 7.3.2 IBM zBX firmware
      4. 7.4 IBM zBX connectivity
        1. 7.4.1 Intranode management network
        2. 7.4.2 Primary and alternate HMCs
        3. 7.4.3 Intraensemble data network
        4. 7.4.4 Network connectivity rules with zBX
        5. 7.4.5 Network security considerations with zBX
        6. 7.4.6 IBM zBX storage connectivity
      5. 7.5 IBM zBX connectivity examples
        1. 7.5.1 A single node ensemble with a zBX
        2. 7.5.2 Dual node ensemble with a single zBX
        3. 7.5.3 Dual node ensemble with two zBXs
      6. 7.6 References
    11. Chapter 8. Software support
      1. 8.1 Operating systems summary
      2. 8.2 Support by operating system
        1. 8.2.1 IBM z/OS
        2. 8.2.2 IBM z/VM
        3. 8.2.3 IBM z/VSE
        4. 8.2.4 IBM z/TPF
        5. 8.2.5 Linux on System z
        6. 8.2.6 IBM zBC12 functions support summary
      3. 8.3 Support by function
        1. 8.3.1 Single system image
        2. 8.3.2 IBM zAAP support
        3. 8.3.3 IBM zIIP support
        4. 8.3.4 The zAAP on zIIP capability
        5. 8.3.5 Transactional Execution
        6. 8.3.6 Maximum main storage size
        7. 8.3.7 Flash Express
        8. 8.3.8 IBM zEnterprise Data Compression Express
        9. 8.3.9 10GbE RoCE Express
        10. 8.3.10 Large page support
        11. 8.3.11 Guest support for execute-extensions facility
        12. 8.3.12 Hardware decimal floating point
        13. 8.3.13 Up to 30 logical partitions
        14. 8.3.14 Separate LPAR management of PUs
        15. 8.3.15 Dynamic LPAR memory upgrade
        16. 8.3.16 LPAR physical capacity limit enforcement
        17. 8.3.17 Capacity Provisioning Manager
        18. 8.3.18 Dynamic PU add
        19. 8.3.19 HiperDispatch
        20. 8.3.20 The 63.75-KB Subchannels
        21. 8.3.21 Multiple subchannel sets
        22. 8.3.22 IPL from an alternate subchannel set
        23. 8.3.23 MIDAW facility
        24. 8.3.24 HiperSockets Completion Queue
        25. 8.3.25 HiperSockets integration with the intraensemble data network
        26. 8.3.26 HiperSockets Virtual Switch Bridge
        27. 8.3.27 HiperSockets Multiple Write Facility
        28. 8.3.28 HiperSockets IPv6
        29. 8.3.29 HiperSockets Layer 2 support
        30. 8.3.30 HiperSockets network traffic analyzer for Linux on System z
        31. 8.3.31 FICON Express8S
        32. 8.3.32 FICON Express8
        33. 8.3.33 IBM z/OS discovery and autoconfiguration
        34. 8.3.34 High performance FICON
        35. 8.3.35 Request node identification data
        36. 8.3.36 24k subchannels for the FICON Express
        37. 8.3.37 Extended distance FICON
        38. 8.3.38 Platform and name server registration in FICON channel
        39. 8.3.39 FICON link incident reporting
        40. 8.3.40 FCP provides increased performance
        41. 8.3.41 N-Port ID virtualization
        42. 8.3.42 OSA-Express5S 10-Gigabit Ethernet LR and SR
        43. 8.3.43 OSA-Express5S Gigabit Ethernet LX and SX
        44. 8.3.44 OSA-Express5S 1000BASE-T Ethernet
        45. 8.3.45 OSA-Express4S 10-Gigabit Ethernet LR and SR
        46. 8.3.46 OSA-Express4S Gigabit Ethernet LX and SX
        47. 8.3.47 OSA-Express3 10-Gigabit Ethernet LR and SR
        48. 8.3.48 OSA-Express3 Gigabit Ethernet LX and SX
        49. 8.3.49 OSA-Express3 1000BASE-T Ethernet
        50. 8.3.50 OSA for IBM zAware
        51. 8.3.51 Open Systems Adapter for Ensemble
        52. 8.3.52 Intranode management network
        53. 8.3.53 Intraensemble data network
        54. 8.3.54 OSA-Express5S and OSA-Express4S NCP support (OSN)
        55. 8.3.55 Integrated Console Controller
        56. 8.3.56 VLAN management enhancements
        57. 8.3.57 GARP VLAN Registration Protocol
        58. 8.3.58 Inbound workload queuing for OSA-Express5S, OSA-Express4S, and OSA-Express3
        59. 8.3.59 Inbound workload queuing for Enterprise Extender
        60. 8.3.60 Query and display OSA configuration
        61. 8.3.61 Link aggregation support for z/VM
        62. 8.3.62 QDIO data connection isolation for z/VM
        63. 8.3.63 QDIO interface isolation for z/OS
        64. 8.3.64 QDIO optimized latency mode
        65. 8.3.65 Large send for IPv6 packets
        66. 8.3.66 OSA-Express5S and OSA-Express4S checksum offload
        67. 8.3.67 Checksum offload for IPv4 packets when in QDIO mode
        68. 8.3.68 Adapter interruptions for QDIO
        69. 8.3.69 OSA Dynamic LAN idle
        70. 8.3.70 OSA Layer 3 Virtual MAC for z/OS environments
        71. 8.3.71 QDIO Diagnostic Synchronization
        72. 8.3.72 Network Traffic Analyzer
        73. 8.3.73 Program-directed re-IPL
        74. 8.3.74 Coupling over InfiniBand
        75. 8.3.75 Dynamic I/O support for InfiniBand CHPIDs
      4. 8.4 Cryptographic Support
        1. 8.4.1 CP Assist for Cryptographic Function
        2. 8.4.2 Crypto Express4S
        3. 8.4.3 Crypto Express3 and Crypto Express3-1P
        4. 8.4.4 Web deliverables
        5. 8.4.5 IBM z/OS Integrated Cryptographic Service Facility FMIDs
        6. 8.4.6 ICSF migration considerations
      5. 8.5 IBM z/OS migration considerations
        1. 8.5.1 General guidelines
        2. 8.5.2 Hardware Configuration Definition
        3. 8.5.3 InfiniBand coupling links
        4. 8.5.4 Large page support
        5. 8.5.5 HiperDispatch
        6. 8.5.6 Capacity Provisioning Manager
        7. 8.5.7 Decimal floating point and z/OS XL C/C++ considerations
        8. 8.5.8 IBM System z Advanced Workload Analysis Reporter
      6. 8.6 Coupling facility and CFCC considerations
      7. 8.7 MIDAW facility
        1. 8.7.1 MIDAW technical description
        2. 8.7.2 Extended format data sets
        3. 8.7.3 Performance benefits
      8. 8.8 Input/output configuration program
      9. 8.9 Worldwide port name tool
      10. 8.10 Device Support Facilities
      11. 8.11 IBM zBX Model 003 software support
        1. 8.11.1 IBM Blades
        2. 8.11.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
      12. 8.12 Software licensing considerations
        1. 8.12.1 MLC pricing metrics
        2. 8.12.2 Advanced workload license charges
        3. 8.12.3 Advanced entry workload license charges
        4. 8.12.4 System z new application license charges
        5. 8.12.5 Select application license charges
        6. 8.12.6 Midrange workload license charges
        7. 8.12.7 Parallel Sysplex license charges
        8. 8.12.8 System z International Program License Agreement
      13. 8.13 References
    12. Chapter 9. System upgrades
      1. 9.1 Upgrade types
        1. 9.1.1 Overview of upgrade types
        2. 9.1.2 Terminology related to CoD for zBC12 systems
        3. 9.1.3 Permanent upgrades
        4. 9.1.4 Temporary upgrades
      2. 9.2 Concurrent upgrades
        1. 9.2.1 Model upgrades
        2. 9.2.2 Customer Initiated Upgrade facility
        3. 9.2.3 Summary of concurrent upgrade functions
      3. 9.3 Miscellaneous equipment specification upgrades
        1. 9.3.1 MES upgrade for processors
        2. 9.3.2 MES upgrade for memory
        3. 9.3.3 Preplanned Memory feature
        4. 9.3.4 MES upgrades for the zBX
      4. 9.4 Permanent upgrade through the CIU facility
        1. 9.4.1 Ordering
        2. 9.4.2 Retrieval and activation
      5. 9.5 On/Off Capacity on Demand
        1. 9.5.1 Overview
        2. 9.5.2 Ordering
        3. 9.5.3 On/Off CoD testing
        4. 9.5.4 Activation and deactivation
        5. 9.5.5 Termination
        6. 9.5.6 IBM z/OS capacity provisioning
      6. 9.6 Capacity for Planned Event
      7. 9.7 Capacity BackUp
        1. 9.7.1 Ordering
        2. 9.7.2 CBU activation and deactivation
        3. 9.7.3 Automatic CBU for Geographically Dispersed Parallel Sysplex
      8. 9.8 Nondisruptive upgrades
      9. 9.9 Summary of capacity on demand offerings
    13. Chapter 10. Reliability, availability, and serviceability
      1. 10.1 IBM zBC12 availability characteristics
      2. 10.2 IBM zBC12 RAS functions
        1. 10.2.1 Scheduled outages
        2. 10.2.2 Unscheduled outages
      3. 10.3 IBM zBC12 enhanced driver maintenance
      4. 10.4 RAS capability for the HMC and SE
      5. 10.5 RAS capability for zBX
      6. 10.6 Considerations for IBM PowerHA in a zBX environment
      7. 10.7 IBM System z Advanced Workload Analysis Reporter
      8. 10.8 RAS capability for Flash Express
    14. Chapter 11. Environmental requirements
      1. 11.1 IBM zBC12 power and cooling
        1. 11.1.1 Power consumption
        2. 11.1.2 Internal Battery Feature
        3. 11.1.3 Emergency power-off
        4. 11.1.4 Cooling requirements
      2. 11.2 IBM zBC12 physical specifications
        1. 11.2.1 Weights and dimensions
        2. 11.2.2 Three-in-one (3-in-1) bolt-down kit
      3. 11.3 IBM zBX environmental components
        1. 11.3.1 IBM zBX configurations
        2. 11.3.2 IBM zBX power components
        3. 11.3.3 IBM zBX cooling
        4. 11.3.4 IBM zBX physical specifications
      4. 11.4 Energy management
        1. 11.4.1 Power estimation tool
        2. 11.4.2 Query maximum potential power
        3. 11.4.3 System Activity Display and Monitors Dashboard
        4. 11.4.4 IBM Systems Director Active Energy Manager
        5. 11.4.5 Unified Resource Manager: Energy management
    15. Chapter 12. Hardware Management Console and Support Element
      1. 12.1 Introduction to HMC and SE
      2. 12.2 SE driver support with new HMC
        1. 12.2.1 HMC FC 0092 changes
      3. 12.3 HMC and SE enhancements and changes
        1. 12.3.1 HMC media support
        2. 12.3.2 Tree Style user interface and Classic Style user interface
      4. 12.4 HMC and SE connectivity
        1. 12.4.1 Hardware prerequisites news
        2. 12.4.2 TCP/IP Version 6 on HMC and SE
        3. 12.4.3 Assigning addresses to HMC and SE
      5. 12.5 Remote Support Facility
        1. 12.5.1 Security characteristics
        2. 12.5.2 RSF connections to IBM and Enhanced IBM Service Support System
        3. 12.5.3 HMC and SE remote operations
      6. 12.6 HMC and SE key capabilities
        1. 12.6.1 Central processor complex management
        2. 12.6.2 Logical partition management
        3. 12.6.3 Operating system communication
        4. 12.6.4 HMC and SE microcode
        5. 12.6.5 Monitoring
        6. 12.6.6 IBM Mobile Systems Remote
        7. 12.6.7 Capacity on demand (CoD) support
        8. 12.6.8 Feature on demand (FoD) support
        9. 12.6.9 Server Time Protocol support
        10. 12.6.10 NTP customer and server support on HMC
        11. 12.6.11 Security and user ID management
        12. 12.6.12 System Input/Output Configuration Analyzer on the SE and HMC
        13. 12.6.13 Automated operations
        14. 12.6.14 Cryptographic support
        15. 12.6.15 IBM z/VM virtual machine management
        16. 12.6.16 Installation support for z/VM using the HMC
      7. 12.7 HMC in an ensemble
        1. 12.7.1 Unified Resource Manager
        2. 12.7.2 Ensemble definition and management
        3. 12.7.3 HMC availability
        4. 12.7.4 Considerations for multiple HMCs
        5. 12.7.5 HMC browser session to a primary HMC
        6. 12.7.6 HMC ensemble topology
    16. Chapter 13. Performance
      1. 13.1 LSPR workload suite
      2. 13.2 Fundamental components of workload capacity performance
      3. 13.3 Relative nest intensity
      4. 13.4 LSPR workload categories based on relative nest intensity
      5. 13.5 Relating production workloads to LSPR workloads
      6. 13.6 Workload performance variation
    17. Appendix A. IBM zAware
      1. Troubleshooting in complex IT environments
      2. Introducing the IBM zAware
      3. IBM zAware Technology
      4. IBM zAware prerequisites
      5. Configuring and using the IBM zAware virtual appliance
    18. Appendix B. Channel options
    19. Appendix C. Flash Express
      1. Flash Express overview
      2. Using Flash Express
      3. Security on Flash Express
    20. Appendix D. Valid zBC12 On/Off Capacity on Demand upgrades
    21. Appendix E. RoCE
      1. Overview
      2. Hardware
      3. Software exploitation
    22. Appendix F. IBM zEnterprise Data Compression Express
      1. Overview
      2. IBM zEDC Express
      3. Software support
    23. Appendix G. Native PCI/e
      1. Design of native PCIe input/output adapter management
      2. About native PCIe
      3. Integrated firmware processor
      4. Resource group
      5. Native PCIe feature plugging rules
      6. Management tasks
      7. IBM zEDC Express
      8. 10GbE RoCE Express
      9. Defining native PCIe features
    24. Appendix H. IBM System z10 Business Class to IBM zEnterprise BC12 upgrade checklist
    25. Related publications
      1. IBM Redbooks publications
      2. Other publications
      3. Online resources
      4. How to get IBM Redbooks publications
      5. Help from IBM
    26. Back cover

    Product information

    • Title: IBM zEnterprise BC12 Technical Guide
    • Author(s): Octavian Lascu, Hua Bin Chu, Ivan Dobos, Luiz Fadel, Wolfgang Fries, Parwez Hamid, Fernando E Nogal, Frank Packheiser, Ewerson Palacio, Martijn Raave, Vicente Ranieri Jr., Andre Spahni, Chen Zhu
    • Release date: February 2014
    • Publisher(s): IBM Redbooks
    • ISBN: None

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