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IBM zEnterprise 196 Technical Guide

Book Description

The popularity of the Internet and the affordability of IT hardware and software have resulted in an explosion of applications, architectures, and platforms. Workloads have changed. Many applications, including mission-critical ones, are deployed on a variety of platforms, and the System z® design has adapted to this change. It takes into account a wide range of factors, including compatibility and investment protection, to match the IT requirements of an enterprise.

The zEnterprise System consists of the IBM zEnterprise 196 central processor complex, the IBM zEnterprise Unified Resource Manager, and the IBM zEnterprise BladeCenter® Extension. The z196 is designed with improved scalability, performance, security, resiliency, availability, and virtualization.

The z196 Model M80 provides up to 1.6 times the total system capacity of the z10™ EC Model E64, and all z196 models provide up to twice the available memory of the z10 EC. The zBX infrastructure works with the z196 to enhance System z virtualization and management through an integrated hardware platform that spans mainframe, POWER7™, and System x® technologies. Through the Unified Resource Manager, the zEnterprise System is managed as a single pool of resources, integrating system and workload management across the environment.

This IBM® Redbooks® publication provides an overview of the zEnterprise System and its functions, features, and associated software support. Greater detail is offered in areas relevant to technical planning. This book is intended for systems engineers, consultants, planners, and anyone wanting to understand the zEnterprise System functions and plan for their usage. It is not intended as an introduction to mainframes. Readers are expected to be generally familiar with existing IBM System z technology and terminology.

The changes to this edition are based on the System z hardware announcement dated July 12, 2011.

Table of Contents

  1. Front cover
  2. Notices
    1. Trademarks
  3. Preface
    1. The team who wrote this book
    2. Now you can become a published author, too!
    3. Comments welcome
    4. Stay connected to IBM Redbooks publications
  4. Chapter 1. Introducing the IBM zEnterprise 196
    1. 1.1 zEnterprise 196 elements
    2. 1.2 zEnterprise 196 highlights
      1. 1.2.1 Models
      2. 1.2.2 Capacity on Demand (CoD)
    3. 1.3 zEnterprise 196 models
      1. 1.3.1 Model upgrade paths
      2. 1.3.2 Concurrent processor unit conversions
    4. 1.4 System functions and features
      1. 1.4.1 Overview
      2. 1.4.2 Processor
      3. 1.4.3 Memory subsystem and topology
      4. 1.4.4 Processor cage
      5. 1.4.5 I/O connectivity, PCIe, and InfiniBand
      6. 1.4.6 I/O subsystems
      7. 1.4.7 Cryptography
      8. 1.4.8 Parallel Sysplex support
    5. 1.5 IBM zEnterprise BladeCenter Extension (zBX)
      1. 1.5.1 Blades
      2. 1.5.2 IBM Smart Analytics Optimizer solution
      3. 1.5.3 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    6. 1.6 Unified Resource Manager
    7. 1.7 Hardware Management Consoles and Support Elements
    8. 1.8 Reliability, availability, and serviceability
    9. 1.9 Performance
      1. 1.9.1 LSPR workload suite
      2. 1.9.2 Fundamental components of workload capacity performance
      3. 1.9.3 Relative nest intensity
      4. 1.9.4 LSPR workload categories based on relative nest intensity
      5. 1.9.5 Relating production workloads to LSPR workloads
      6. 1.9.6 Workload performance variation
    10. 1.10 Operating systems and software
  5. Chapter 2. CPC hardware components
    1. 2.1 Frames and cage
      1. 2.1.1 Frame A
      2. 2.1.2 Frame Z
      3. 2.1.3 I/O cages, I/O drawers, and PCIe I/O drawers
      4. 2.1.4 Top exit I/O cabling
    2. 2.2 Book concept
      1. 2.2.1 Book interconnect topology
      2. 2.2.2 Oscillator
      3. 2.2.3 System control
      4. 2.2.4 Book power
    3. 2.3 Multi-chip module
    4. 2.4 Processor units and storage control chips
      1. 2.4.1 PU chip
      2. 2.4.2 Processor unit (core)
      3. 2.4.3 PU characterization
      4. 2.4.4 Storage control (SC) chip
      5. 2.4.5 Cache level structure
    5. 2.5 Memory
      1. 2.5.1 Memory subsystem topology
      2. 2.5.2 Redundant array of independent memory (RAIM)
      3. 2.5.3 Memory configurations
      4. 2.5.4 Memory upgrades
      5. 2.5.5 Book replacement and memory
      6. 2.5.6 Flexible Memory Option
      7. 2.5.7 Preplanned Memory
    6. 2.6 Reliability, availability, serviceability (RAS)
    7. 2.7 Connectivity
      1. 2.7.1 Redundant I/O interconnect
      2. 2.7.2 Enhanced book availability
      3. 2.7.3 Book upgrade
    8. 2.8 Model configurations
      1. 2.8.1 Upgrades
      2. 2.8.2 Concurrent PU conversions
      3. 2.8.3 Model capacity identifier
      4. 2.8.4 Model capacity identifier and MSU values
      5. 2.8.5 Capacity Backup
      6. 2.8.6 On/Off Capacity on Demand and CPs
    9. 2.9 Power and cooling
      1. 2.9.1 Power consumption
      2. 2.9.2 High voltage DC power
      3. 2.9.3 Internal Battery Feature (IBF)
      4. 2.9.4 Power capping and power saving
      5. 2.9.5 Power estimation tool
      6. 2.9.6 Cooling
      7. 2.9.7 Air cooled models
      8. 2.9.8 Water cooled models
    10. 2.10 Summary of z196 structure
  6. Chapter 3. CPC system design
    1. 3.1 Design highlights
    2. 3.2 Book design
      1. 3.2.1 Cache levels and memory structure
      2. 3.2.2 Book interconnect topology
    3. 3.3 Processor unit design
      1. 3.3.1 Out-of-order execution
      2. 3.3.2 Superscalar processor
      3. 3.3.3 Compression and cryptography accelerators on a chip
      4. 3.3.4 Decimal floating point accelerator
      5. 3.3.5 Processor error detection and recovery
      6. 3.3.6 Branch prediction
      7. 3.3.7 Wild branch
      8. 3.3.8 IEEE floating point
      9. 3.3.9 Translation look-aside buffer
      10. 3.3.10 Instruction fetching, decode, and grouping
      11. 3.3.11 Extended translation facility
      12. 3.3.12 Instruction set extensions
    4. 3.4 Processor unit functions
      1. 3.4.1 Overview
      2. 3.4.2 Central processors
      3. 3.4.3 Integrated Facility for Linux
      4. 3.4.4 Internal Coupling Facility
      5. 3.4.5 System z Application Assist Processors
      6. 3.4.6 System z Integrated Information Processor
      7. 3.4.7 zAAP on zIIP capability
      8. 3.4.8 System Assist Processors
      9. 3.4.9 Reserved processors
      10. 3.4.10 Processor unit assignment
      11. 3.4.11 Sparing rules
      12. 3.4.12 Increased flexibility with z/VM-mode partitions
    5. 3.5 Memory design
      1. 3.5.1 Overview
      2. 3.5.2 Central storage
      3. 3.5.3 Expanded storage
      4. 3.5.4 Hardware system area
    6. 3.6 Logical partitioning
      1. 3.6.1 Overview
      2. 3.6.2 Storage operations
      3. 3.6.3 Reserved storage
      4. 3.6.4 Logical partition storage granularity
      5. 3.6.5 LPAR dynamic storage reconfiguration
    7. 3.7 Intelligent resource director
    8. 3.8 Clustering technology
      1. 3.8.1 Coupling facility control code
      2. 3.8.2 Dynamic CF dispatching
  7. Chapter 4. CPC I/O system structure
    1. 4.1 Introduction
      1. 4.1.1 Infrastructure types
      2. 4.1.2 InfiniBand specification
      3. 4.1.3 Data, signalling, and link rates
      4. 4.1.4 PCIe
    2. 4.2 I/O system overview
      1. 4.2.1 Characteristics
      2. 4.2.2 Summary of supported I/O features
    3. 4.3 I/O cages
    4. 4.4 I/O drawers
    5. 4.5 PCIe I/O drawers
    6. 4.6 I/O cage, I/O drawer and PCIe I/O drawer offerings
    7. 4.7 Fanouts
      1. 4.7.1 HCA2-C fanout
      2. 4.7.2 PCIe copper fanout
      3. 4.7.3 HCA2-O (12xIFB) fanout
      4. 4.7.4 HCA2-O LR (1xIFB) fanout
      5. 4.7.5 HCA3-O (12xIFB) fanout
      6. 4.7.6 HCA3-O LR (1xIFB) fanout
      7. 4.7.7 Fanout considerations
      8. 4.7.8 Fanout summary
    8. 4.8 I/O feature cards
      1. 4.8.1 I/O feature card types ordering information
      2. 4.8.2 PCHID report
    9. 4.9 Connectivity
      1. 4.9.1 I/O feature support and configuration rules
      2. 4.9.2 ESCON channels
      3. 4.9.3 FICON channels
      4. 4.9.4 OSA-Express4S
      5. 4.9.5 OSA-Express3
      6. 4.9.6 OSA-Express2
      7. 4.9.7 OSA-Express for ensemble connectivity
      8. 4.9.8 HiperSockets
    10. 4.10 Parallel Sysplex connectivity
      1. 4.10.1 Coupling links
      2. 4.10.2 External clock facility
    11. 4.11 Cryptographic functions
      1. 4.11.1 CPACF functions (FC 3863)
      2. 4.11.2 Crypto Express3 feature (FC 0864)
  8. Chapter 5. CPC channel subsystem
    1. 5.1 Channel subsystem
      1. 5.1.1 Multiple CSSs concept
      2. 5.1.2 CSS elements
      3. 5.1.3 Multiple subchannel sets
      4. 5.1.4 Parallel access volumes and extended address volumes
      5. 5.1.5 Logical partition name and identification
      6. 5.1.6 Physical channel ID
      7. 5.1.7 Channel spanning
      8. 5.1.8 Multiple CSS construct
      9. 5.1.9 Adapter ID
    2. 5.2 I/O configuration management
    3. 5.3 Channel subsystem summary
    4. 5.4 System-initiated CHPID reconfiguration
    5. 5.5 Multipath initial program load
  9. Chapter 6. Cryptography
    1. 6.1 Cryptographic synchronous functions
    2. 6.2 Cryptographic asynchronous functions
      1. 6.2.1 Secure key functions
      2. 6.2.2 CPACF protected key
      3. 6.2.3 Other key functions
      4. 6.2.4 Cryptographic feature codes
    3. 6.3 CP Assist for Cryptographic Function
    4. 6.4 Crypto Express3
      1. 6.4.1 Crypto Express3 coprocessor
      2. 6.4.2 Crypto Express3 accelerator
      3. 6.4.3 Configuration rules
    5. 6.5 TKE workstation feature
      1. 6.5.1 Logical partition, TKE host, and TKE target
      2. 6.5.2 Optional smart card reader
    6. 6.6 Cryptographic functions comparison
    7. 6.7 Software support
  10. Chapter 7. zEnterprise BladeCenter Extension Model 002
    1. 7.1 zBX concepts
    2. 7.2 zBX hardware description
      1. 7.2.1 zBX racks
      2. 7.2.2 Top of rack (TOR) switches
      3. 7.2.3 zBX BladeCenter chassis
      4. 7.2.4 zBX blades
      5. 7.2.5 Power distribution unit (PDU)
    3. 7.3 zBX entitlements and firmware
      1. 7.3.1 zBX management
      2. 7.3.2 zBX firmware
    4. 7.4 zBX connectivity
      1. 7.4.1 Intranode management network
      2. 7.4.2 Primary and alternate HMCs
      3. 7.4.3 Intraensemble data network
      4. 7.4.4 Network connectivity rules with zBX
      5. 7.4.5 Network security considerations with zBX
      6. 7.4.6 zBX storage connectivity
    5. 7.5 zBX connectivity examples
      1. 7.5.1 A single node ensemble with a zBX
      2. 7.5.2 A dual node ensemble with a single zBX
      3. 7.5.3 A dual node ensemble with two zBXs
    6. 7.6 References
  11. Chapter 8. Software support
    1. 8.1 Operating systems summary
    2. 8.2 Support by operating system
      1. 8.2.1 z/OS
      2. 8.2.2 z/VM
      3. 8.2.3 z/VSE
      4. 8.2.4 z/TPF
      5. 8.2.5 Linux on System z
      6. 8.2.6 z196 functions support summary
    3. 8.3 Support by function
      1. 8.3.1 Single system image
      2. 8.3.2 zAAP support
      3. 8.3.3 zIIP support
      4. 8.3.4 zAAP on zIIP capability
      5. 8.3.5 Maximum main storage size
      6. 8.3.6 Large page support
      7. 8.3.7 Guest support for execute-extensions facility
      8. 8.3.8 Hardware decimal floating point
      9. 8.3.9 Up to 60 logical partitions
      10. 8.3.10 Separate LPAR management of PUs
      11. 8.3.11 Dynamic LPAR memory upgrade
      12. 8.3.12 Capacity Provisioning Manager
      13. 8.3.13 Dynamic PU add
      14. 8.3.14 HiperDispatch
      15. 8.3.15 The 63.75 K subchannels
      16. 8.3.16 Multiple subchannel sets
      17. 8.3.17 Third subchannel set
      18. 8.3.18 IPL from an alternate subchannel set
      19. 8.3.19 MIDAW facility
      20. 8.3.20 Enhanced CPACF
      21. 8.3.21 HiperSockets multiple write facility
      22. 8.3.22 HiperSockets IPv6
      23. 8.3.23 HiperSockets Layer 2 support
      24. 8.3.24 HiperSockets network traffic analyzer for Linux on System z
      25. 8.3.25 HiperSockets statements of direction
      26. 8.3.26 FICON Express8S
      27. 8.3.27 FICON Express8
      28. 8.3.28 z/OS discovery and autoconfiguration (zDAC)
      29. 8.3.29 High performance FICON (zHPF)
      30. 8.3.30 Request node identification data
      31. 8.3.31 Extended distance FICON
      32. 8.3.32 Platform and name server registration in FICON channel
      33. 8.3.33 FICON link incident reporting
      34. 8.3.34 FCP provides increased performance
      35. 8.3.35 N_Port ID virtualization
      36. 8.3.36 OSA-Express4S 10 Gigabit Ethernet LR and SR
      37. 8.3.37 OSA-Express4S Gigabit Ethernet LX and SX
      38. 8.3.38 OSA-Express3 10 Gigabit Ethernet LR and SR
      39. 8.3.39 OSA-Express3 Gigabit Ethernet LX and SX
      40. 8.3.40 OSA-Express3 1000BASE-T Ethernet
      41. 8.3.41 OSA-Express2 1000BASE-T Ethernet
      42. 8.3.42 Open Systems Adapter for Ensemble
      43. 8.3.43 Intranode management network (INMN)
      44. 8.3.44 Intraensemble data network (IEDN)
      45. 8.3.45 OSA-Express3 and OSA-Express2 NCP support (OSN)
      46. 8.3.46 Integrated Console Controller
      47. 8.3.47 VLAN management enhancements
      48. 8.3.48 GARP VLAN Registration Protocol
      49. 8.3.49 Inbound workload queueing (IWQ) for OSA-Express4S and OSA-Express3
      50. 8.3.50 Inbound workload queueing (IWQ) for Enterprise Extender
      51. 8.3.51 Query and display OSA configuration
      52. 8.3.52 Link aggregation support for z/VM
      53. 8.3.53 QDIO data connection isolation for z/VM
      54. 8.3.54 QDIO interface isolation for z/OS
      55. 8.3.55 QDIO optimized latency mode
      56. 8.3.56 OSA-Express4S checksum offload
      57. 8.3.57 Checksum offload for IPv4 packets when in QDIO mode
      58. 8.3.58 Adapter interruptions for QDIO
      59. 8.3.59 OSA Dynamic LAN idle
      60. 8.3.60 OSA Layer 3 Virtual MAC for z/OS environments
      61. 8.3.61 QDIO Diagnostic Synchronization
      62. 8.3.62 Network Traffic Analyzer
      63. 8.3.63 Program directed re-IPL
      64. 8.3.64 Coupling over InfiniBand
      65. 8.3.65 Dynamic I/O support for InfiniBand CHPIDs
    4. 8.4 Cryptographic support
      1. 8.4.1 CP Assist for Cryptographic Function
      2. 8.4.2 Crypto Express3
      3. 8.4.3 Web deliverables
      4. 8.4.4 z/OS ICSF FMIDs
      5. 8.4.5 ICSF migration considerations
    5. 8.5 z/OS migration considerations
      1. 8.5.1 General guidelines
      2. 8.5.2 HCD
      3. 8.5.3 InfiniBand coupling links
      4. 8.5.4 Large page support
      5. 8.5.5 HiperDispatch
      6. 8.5.6 Capacity Provisioning Manager
      7. 8.5.7 Decimal floating point and z/OS XL C/C++ considerations
    6. 8.6 Coupling facility and CFCC considerations
    7. 8.7 MIDAW facility
      1. 8.7.1 MIDAW technical description
      2. 8.7.2 Extended format data sets
      3. 8.7.3 Performance benefits
    8. 8.8 IOCP
    9. 8.9 Worldwide portname (WWPN) tool
    10. 8.10 ICKDSF
    11. 8.11 zEnterprise BladeCenter Extension software support
      1. 8.11.1 IBM Blades
      2. 8.11.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
      3. 8.11.3 IBM Smart Analytics Optimizer solution
    12. 8.12 Software licensing considerations
      1. 8.12.1 MLC pricing metrics
      2. 8.12.2 Advanced Workload License Charges (AWLC)
      3. 8.12.3 Advanced Entry Workload License Charges (AEWLC)
      4. 8.12.4 System z New Application License Charges (zNALC)
      5. 8.12.5 Select Application License Charges (SALC)
      6. 8.12.6 Midrange Workload Licence Charges (MWLC)
      7. 8.12.7 Parallel Sysplex Licence Charges (PWLC)
      8. 8.12.8 System z International Program License Agreement (IPLA)
    13. 8.13 References
  12. Chapter 9. System upgrades
    1. 9.1 Upgrade types
      1. 9.1.1 Overview
      2. 9.1.2 Permanent upgrades
      3. 9.1.3 Temporary upgrades
    2. 9.2 Concurrent upgrades
      1. 9.2.1 Model upgrades
      2. 9.2.2 Customer Initiated Upgrade facility
      3. 9.2.3 Summary of concurrent upgrade functions
    3. 9.3 MES upgrades
      1. 9.3.1 MES upgrade for processors
      2. 9.3.2 MES upgrades for memory
      3. 9.3.3 MES upgrades for I/O
      4. 9.3.4 MES upgrades for the zBX
      5. 9.3.5 Plan-ahead concurrent conditioning
    4. 9.4 Permanent upgrade through the CIU facility
      1. 9.4.1 Ordering
      2. 9.4.2 Retrieval and activation
    5. 9.5 On/Off Capacity on Demand
      1. 9.5.1 Overview
      2. 9.5.2 Ordering
      3. 9.5.3 On/Off CoD testing
      4. 9.5.4 Activation and deactivation
      5. 9.5.5 Termination
      6. 9.5.6 z/OS capacity provisioning
    6. 9.6 Capacity for Planned Event
    7. 9.7 Capacity Backup
      1. 9.7.1 Ordering
      2. 9.7.2 CBU activation and deactivation
      3. 9.7.3 Automatic CBU enablement for GDPS
    8. 9.8 Nondisruptive upgrades
      1. 9.8.1 Components
      2. 9.8.2 Concurrent upgrade considerations
    9. 9.9 Summary of Capacity on Demand offerings
    10. 9.10 References
  13. Chapter 10. RAS
    1. 10.1 z196 availability characteristics
    2. 10.2 z196 RAS functions
      1. 10.2.1 Scheduled outages
      2. 10.2.2 Unscheduled outages
    3. 10.3 z196 Enhanced book availability
      1. 10.3.1 EBA planning considerations
      2. 10.3.2 Enhanced book availability processing
    4. 10.4 z196 Enhanced driver maintenance
    5. 10.5 RAS capability for the HMC in an ensemble
    6. 10.6 RAS capability for zBX
      1. 10.6.1 BladeCenter components
      2. 10.6.2 zBX firmware
      3. 10.6.3 zBX RAS and the Unified Resource Manager
    7. 10.7 Considerations for PowerHA in zBX environment
  14. Chapter 11. Environmental requirements
    1. 11.1 z196 power and cooling
      1. 11.1.1 Power consumption
      2. 11.1.2 Internal Battery Feature
      3. 11.1.3 Emergency power-off
      4. 11.1.4 Cooling requirements
    2. 11.2 z196 physical specifications
      1. 11.2.1 Weights and dimensions
      2. 11.2.2 Weight distribution plate
      3. 11.2.3 3-in-1 bolt down kit for raised floor
    3. 11.3 zBX environmentals
      1. 11.3.1 zBX configurations
      2. 11.3.2 zBX power components
      3. 11.3.3 zBX cooling
      4. 11.3.4 zBX physical specifications
    4. 11.4 Energy management
      1. 11.4.1 Power estimation tool
      2. 11.4.2 Query maximum potential power
      3. 11.4.3 System Activity Display and Monitors Dashboard
      4. 11.4.4 IBM Systems Director Active Energy Manager
      5. 11.4.5 Unified Resource Manager: Energy Management
  15. Chapter 12. Hardware Management Console
    1. 12.1 Introduction to HMC and SE
      1. 12.1.1 Support summary
      2. 12.1.2 Tree Style User Interface and Classic Style User Interface
    2. 12.2 HMC and SE connectivity
      1. 12.2.1 TCP/IP Version 6 on HMC and SE
      2. 12.2.2 Assigning addresses to HMC and SE
    3. 12.3 Remote Support Facility
    4. 12.4 HMC remote operations
      1. 12.4.1 Using a remote HMC
      2. 12.4.2 Using a web browser
    5. 12.5 HMC media support
    6. 12.6 HMC and SE key capabilities
      1. 12.6.1 CPC management
      2. 12.6.2 LPAR management
      3. 12.6.3 Operating system communication
      4. 12.6.4 SE access
      5. 12.6.5 Monitoring
      6. 12.6.6 Capacity on Demand support
      7. 12.6.7 Server Time Protocol support
      8. 12.6.8 NTP client/server support on HMC
      9. 12.6.9 Security and User ID Management
      10. 12.6.10 System Input/Output Configuration Analyzer on the SE/HMC
      11. 12.6.11 Test Support Element Communications
      12. 12.6.12 Automated operations
      13. 12.6.13 Cryptographic support
      14. 12.6.14 z/VM virtual machine management
      15. 12.6.15 Installation support for z/VM using the HMC
    7. 12.7 HMC in an ensemble
      1. 12.7.1 Unified Resource Manager
      2. 12.7.2 Ensemble definition and management
      3. 12.7.3 HMC availability
      4. 12.7.4 Considerations for multiple HMCs
      5. 12.7.5 HMC browser session to a primary HMC
      6. 12.7.6 HMC ensemble topology
  16. Appendix A. Channel options
  17. Related publications
    1. IBM Redbooks publications
    2. Other publications
    3. Online resources
    4. How to get Redbooks publications
    5. Help from IBM
  18. Back cover