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IBM z13 Technical Guide

Book Description

Digital business has been driving the transformation of underlying IT infrastructure to be more efficient, secure, adaptive, and integrated. Information Technology (IT) must be able to handle the explosive growth of mobile clients and employees. IT also must be able to use enormous amounts of data to provide deep and real-time insights to help achieve the greatest business impact.

This IBM® Redbooks® publication addresses the new IBM Mainframe, the IBM z13. The IBM z13 is the trusted enterprise platform for integrating data, transactions, and insight. A data-centric infrastructure must always be available with a 99.999% or better availability, have flawless data integrity, and be secured from misuse. It needs to be an integrated infrastructure that can support new applications. It needs to have integrated capabilities that can provide new mobile capabilities with real-time analytics delivered by a secure cloud infrastructure.

IBM z13 is designed with improved scalability, performance, security, resiliency, availability, and virtualization. The superscalar design allows the z13 to deliver a record level of capacity over the prior z Systems. In its maximum configuration, z13 is powered by up to 141 client characterizable microprocessors (cores) running at 5 GHz. This configuration can run more than 110,000 millions of instructions per second (MIPS) and up to 10 TB of client memory. The IBM z13 Model NE1 is estimated to provide up to 40% more total system capacity than the IBM zEnterprise® EC12 (zEC1) Model HA1.

This book provides information about the IBM z13 and its functions, features, and associated software support. Greater detail is offered in areas relevant to technical planning. It is intended for systems engineers, consultants, planners, and anyone who wants to understand the IBM z Systems functions and plan for their usage. It is not intended as an introduction to mainframes. Readers are expected to be generally familiar with existing IBM z Systems technology and terminology.

Table of Contents

  1. Front cover
  2. Notices
    1. Trademarks
  3. IBM Redbooks promotions
  4. Preface
    1. Authors
    2. Now you can become a published author, too!
    3. Comments welcome
    4. Stay connected to IBM Redbooks
  5. Chapter 1. Introducing the IBM z13
    1. 1.1 z13 highlights
      1. 1.1.1 Processor and memory
      2. 1.1.2 Capacity and performance
      3. 1.1.3 I/O subsystem and I/O features
      4. 1.1.4 Virtualization
      5. 1.1.5 Reliability, availability, and serviceability design
    2. 1.2 z13 technical overview
      1. 1.2.1 Models
      2. 1.2.2 Model upgrade paths
      3. 1.2.3 Frames
      4. 1.2.4 CPC drawer
      5. 1.2.5 I/O connectivity: PCIe and InfiniBand
      6. 1.2.6 I/O subsystems
      7. 1.2.7 Coupling and Server Time Protocol connectivity
      8. 1.2.8 Special-purpose features
      9. 1.2.9 Reliability, availability, and serviceability (RAS)
    3. 1.3 Hardware Management Consoles (HMCs) and Support Elements (SEs)
    4. 1.4 IBM z BladeCenter Extension (zBX) Model 004
      1. 1.4.1 Blades
      2. 1.4.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    5. 1.5 IBM z Unified Resource Manager
    6. 1.6 Operating systems and software
      1. 1.6.1 Supported operating systems
      2. 1.6.2 IBM compilers
  6. Chapter 2. Central processor complex (CPC) hardware components
    1. 2.1 Frames and drawers
      1. 2.1.1 A Frame
      2. 2.1.2 Z Frame
      3. 2.1.3 z13 new rear cover (door) design
      4. 2.1.4 I/O drawer and PCIe I/O drawer
      5. 2.1.5 Top exit I/O cabling
    2. 2.2 CPC drawer
      1. 2.2.1 CPC drawer interconnect topology
      2. 2.2.2 Oscillator
      3. 2.2.3 System control
      4. 2.2.4 CPC drawer power
    3. 2.3 Single chip modules (SCMs)
      1. 2.3.1 Processor unit (PU) chip
      2. 2.3.2 Processor unit (core)
      3. 2.3.3 PU characterization
      4. 2.3.4 Storage control (SC) chip
      5. 2.3.5 Cache level structure
    4. 2.4 Memory
      1. 2.4.1 Memory subsystem topology
      2. 2.4.2 Redundant array of independent memory
      3. 2.4.3 Memory configurations
      4. 2.4.4 Memory upgrades
      5. 2.4.5 Drawer replacement and memory
      6. 2.4.6 Flexible Memory Option
      7. 2.4.7 Pre-planned memory
    5. 2.5 Reliability, availability, and serviceability (RAS)
      1. 2.5.1 RAS in the CPC memory subsystem
      2. 2.5.2 General z13 RAS features
    6. 2.6 Connectivity
      1. 2.6.1 Redundant I/O interconnect
      2. 2.6.2 Enhanced drawer availability (EDA)
      3. 2.6.3 CPC drawer upgrade
    7. 2.7 Model configurations
      1. 2.7.1 Upgrades
      2. 2.7.2 Concurrent PU conversions
      3. 2.7.3 Model capacity identifier
      4. 2.7.4 Model capacity identifier and MSU value
      5. 2.7.5 Capacity Backup (CBU)
      6. 2.7.6 On/Off Capacity on Demand and CPs
    8. 2.8 Power and cooling
      1. 2.8.1 Power consumption
      2. 2.8.2 High Voltage Direct Current power feature
      3. 2.8.3 Internal Battery Feature (IBF)
      4. 2.8.4 Power capping and saving
      5. 2.8.5 Power estimation tool
      6. 2.8.6 Cooling
      7. 2.8.7 Radiator Unit
      8. 2.8.8 Water-cooling unit
    9. 2.9 Summary of z13 structure
  7. Chapter 3. Central processor complex system design
    1. 3.1 Overview
    2. 3.2 Design highlights
    3. 3.3 CPC drawer design
      1. 3.3.1 Cache levels and memory structure
      2. 3.3.2 CPC drawer interconnect topology
    4. 3.4 Processor unit design
      1. 3.4.1 Simultaneous multithreading (SMT)
      2. 3.4.2 Single-instruction multiple-data (SIMD)
      3. 3.4.3 Out-of-order (OOO) execution
      4. 3.4.4 Superscalar processor
      5. 3.4.5 Compression and cryptography accelerators on a chip
      6. 3.4.6 Decimal floating point (DFP) accelerator
      7. 3.4.7 IEEE floating point
      8. 3.4.8 Processor error detection and recovery
      9. 3.4.9 Branch prediction
      10. 3.4.10 Wild branch
      11. 3.4.11 Translation lookaside buffer (TLB)
      12. 3.4.12 Instruction fetching, decoding, and grouping
      13. 3.4.13 Extended Translation Facility
      14. 3.4.14 Instruction set extensions
      15. 3.4.15 Transactional Execution
      16. 3.4.16 Runtime Instrumentation
    5. 3.5 Processor unit (PU) functions
      1. 3.5.1 Overview
      2. 3.5.2 Central processors (CPs)
      3. 3.5.3 Integrated Facility for Linux (IFL)
      4. 3.5.4 Internal Coupling Facility (ICF)
      5. 3.5.5 z Systems Integrated Information Processor (zIIP)
      6. 3.5.6 System assist processors
      7. 3.5.7 Reserved processors
      8. 3.5.8 Integrated firmware processor (IFP)
      9. 3.5.9 Processor unit assignment
      10. 3.5.10 Sparing rules
      11. 3.5.11 Increased flexibility with z/VM mode partitions
    6. 3.6 Memory design
      1. 3.6.1 Overview
      2. 3.6.2 Main storage
      3. 3.6.3 Expanded storage
      4. 3.6.4 Hardware system area (HSA)
    7. 3.7 Logical partitioning
      1. 3.7.1 Overview
      2. 3.7.2 Storage operations
      3. 3.7.3 Reserved storage
      4. 3.7.4 Logical partition storage granularity
      5. 3.7.5 LPAR dynamic storage reconfiguration
    8. 3.8 Intelligent Resource Director (IRD)
    9. 3.9 Clustering technology
      1. 3.9.1 Coupling Facility Control Code
      2. 3.9.2 Coupling Thin Interrupts
      3. 3.9.3 Dynamic CF dispatching
      4. 3.9.4 CFCC and Flash Express use
  8. Chapter 4. Central processor complex I/O system structure
    1. 4.1 Introduction to the InfiniBand and PCIe for I/O infrastructure
      1. 4.1.1 InfiniBand specifications
      2. 4.1.2 PCIe Generation 3
    2. 4.2 I/O system overview
      1. 4.2.1 Characteristics
      2. 4.2.2 Summary of supported I/O features
    3. 4.3 I/O drawer
    4. 4.4 PCIe I/O drawer
    5. 4.5 PCIe I/O drawer and I/O drawer offerings
    6. 4.6 Fanouts
      1. 4.6.1 PCIe Generation 3 fanout (FC 0173)
      2. 4.6.2 HCA2-C fanout (FC 0162)
      3. 4.6.3 Integrated Coupling Adapter (FC 0172)
      4. 4.6.4 HCA3-O (12x IFB) fanout (FC 0171)
      5. 4.6.5 HCA3-O LR (1x IFB) fanout (FC 0170)
      6. 4.6.6 Fanout considerations
    7. 4.7 I/O features (cards)
      1. 4.7.1 I/O feature card ordering information
      2. 4.7.2 Physical channel (PCHID) report
    8. 4.8 Connectivity
      1. 4.8.1 I/O feature support and configuration rules
      2. 4.8.2 FICON channels
      3. 4.8.3 OSA-Express5S
      4. 4.8.4 OSA-Express4S features
      5. 4.8.5 OSA-Express for ensemble connectivity
      6. 4.8.6 HiperSockets
    9. 4.9 Parallel Sysplex connectivity
      1. 4.9.1 Coupling links
      2. 4.9.2 Migration considerations
      3. 4.9.3 Pulse Per Second (PPS) input
    10. 4.10 Cryptographic functions
      1. 4.10.1 CPACF functions (FC 3863)
      2. 4.10.2 Crypto Express5S feature (FC 0890)
    11. 4.11 Integrated firmware processor
    12. 4.12 Flash Express
    13. 4.13 10GbE RoCE Express
    14. 4.14 zEDC Express
  9. Chapter 5. Central processor complex channel subsystem
    1. 5.1 Channel subsystem
      1. 5.1.1 Multiple channel subsystems concept
      2. 5.1.2 CSS elements
      3. 5.1.3 Multiple subchannel sets
      4. 5.1.4 Parallel access volumes and extended address volumes
      5. 5.1.5 Logical partition name and identification
      6. 5.1.6 Physical channel ID (PCHID)
      7. 5.1.7 Channel spanning
      8. 5.1.8 Multiple CSSs construct
      9. 5.1.9 Adapter ID (AID)
      10. 5.1.10 Channel subsystem enhancement for I/O resilience
    2. 5.2 I/O configuration management
    3. 5.3 Channel subsystem summary
    4. 5.4 System-initiated CHPID reconfiguration
    5. 5.5 Multipath initial program load
  10. Chapter 6. Cryptography
    1. 6.1 Cryptographic synchronous functions
    2. 6.2 Cryptographic asynchronous functions
      1. 6.2.1 Secure key functions
      2. 6.2.2 Additional functions
    3. 6.3 CPACF protected key
    4. 6.4 PKCS #11 overview
      1. 6.4.1 PKCS #11 model
      2. 6.4.2 z/OS PKCS #11 implementation
      3. 6.4.3 Secure IBM Enterprise PKCS #11 (EP11) Coprocessor
    5. 6.5 Cryptographic feature codes
    6. 6.6 CP Assist for Cryptographic Function (CPACF)
    7. 6.7 Crypto Express5S
    8. 6.8 Tasks that are run by PCIe Crypto Express5S
      1. 6.8.1 PCIe Crypto Express5S as a CCA coprocessor
      2. 6.8.2 PCIe Crypto Express5S as an EP11 coprocessor
      3. 6.8.3 PCIe Crypto Express as an accelerator
      4. 6.8.4 IBM Common Cryptographic Architecture enhancements
    9. 6.9 TKE workstation feature
      1. 6.9.1 TKE workstation with Licensed Internal Code 7.0
      2. 6.9.2 TKE workstation with Licensed Internal Code 7.1
      3. 6.9.3 TKE workstation with Licensed Internal Code 7.2
      4. 6.9.4 TKE workstation with Licensed Internal Code 7.3
      5. 6.9.5 TKE workstation with Licensed Internal Code 8.0
      6. 6.9.6 Logical partition, TKE host, and TKE target
      7. 6.9.7 Optional smart card reader
      8. 6.9.8 TKE hardware support and migration information
    10. 6.10 Cryptographic functions comparison
    11. 6.11 Software support
  11. Chapter 7. Software support
    1. 7.1 Operating systems summary
    2. 7.2 Support by operating system
      1. 7.2.1 z/OS
      2. 7.2.2 z/VM
      3. 7.2.3 z/VSE
      4. 7.2.4 z/TPF
      5. 7.2.5 Linux on z Systems
      6. 7.2.6 z13 function support summary
    3. 7.3 Support by function
      1. 7.3.1 Single system image
      2. 7.3.2 zIIP support
      3. 7.3.3 Transactional Execution
      4. 7.3.4 Maximum main storage size
      5. 7.3.5 Flash Express
      6. 7.3.6 zEnterprise Data Compression Express (zEDC)
      7. 7.3.7 10GbE RoCE Express
      8. 7.3.8 Large page support
      9. 7.3.9 Hardware decimal floating point
      10. 7.3.10 Up to 85 LPARs
      11. 7.3.11 Separate LPAR management of PUs
      12. 7.3.12 Dynamic LPAR memory upgrade
      13. 7.3.13 LPAR physical capacity limit enforcement
      14. 7.3.14 Capacity Provisioning Manager
      15. 7.3.15 Dynamic PU add
      16. 7.3.16 HiperDispatch
      17. 7.3.17 The 63.75-K subchannels
      18. 7.3.18 Multiple subchannel sets (MSS)
      19. 7.3.19 Fourth subchannel set
      20. 7.3.20 IPL from an alternative subchannel set
      21. 7.3.21 Modified Indirect Data Address Word (MIDAW) facility
      22. 7.3.22 HiperSockets Completion Queue
      23. 7.3.23 HiperSockets integration with the intraensemble data network
      24. 7.3.24 HiperSockets Virtual Switch Bridge
      25. 7.3.25 HiperSockets Multiple Write Facility
      26. 7.3.26 HiperSockets IPv6
      27. 7.3.27 HiperSockets Layer 2 support
      28. 7.3.28 HiperSockets network traffic analyzer for Linux on z Systems
      29. 7.3.29 FICON Express16S
      30. 7.3.30 FICON Express8S
      31. 7.3.31 FICON Express8
      32. 7.3.32 z/OS Discovery and Auto-Configuration (zDAC)
      33. 7.3.33 High-performance FICON
      34. 7.3.34 Request node identification data
      35. 7.3.35 32 K subchannels for the FICON Express16S
      36. 7.3.36 Extended distance FICON
      37. 7.3.37 Platform and name server registration in FICON channel
      38. 7.3.38 FICON link incident reporting
      39. 7.3.39 FCP provides increased performance
      40. 7.3.40 N Port ID Virtualization (NPIV)
      41. 7.3.41 OSA-Express5S 10-Gigabit Ethernet LR and SR
      42. 7.3.42 OSA-Express5S Gigabit Ethernet LX and SX
      43. 7.3.43 OSA-Express5S 1000BASE-T Ethernet
      44. 7.3.44 OSA-Express4S 10-Gigabit Ethernet LR and SR
      45. 7.3.45 OSA-Express4S Gigabit Ethernet LX and SX
      46. 7.3.46 OSA-Express4S 1000BASE-T Ethernet
      47. 7.3.47 Open Systems Adapter for IBM zAware
      48. 7.3.48 Open Systems Adapter for Ensemble
      49. 7.3.49 Intranode management network (INMN)
      50. 7.3.50 Intraensemble data network
      51. 7.3.51 OSA-Express5S and OSA-Express4S NCP support
      52. 7.3.52 Integrated Console Controller
      53. 7.3.53 VLAN management enhancements
      54. 7.3.54 GARP VLAN Registration Protocol
      55. 7.3.55 Inbound workload queuing for OSA-Express5S and OSA-Express4S
      56. 7.3.56 Inbound workload queuing for Enterprise Extender
      57. 7.3.57 Querying and displaying an OSA configuration
      58. 7.3.58 Link aggregation support for z/VM
      59. 7.3.59 Multi-VSwitch Link Aggregation
      60. 7.3.60 QDIO data connection isolation for z/VM
      61. 7.3.61 QDIO interface isolation for z/OS
      62. 7.3.62 QDIO optimized latency mode
      63. 7.3.63 Large send for IPv6 packets
      64. 7.3.64 OSA-Express5S and OSA-Express4S checksum offload
      65. 7.3.65 Checksum offload for IPv4and IPv6 packets when in QDIO mode
      66. 7.3.66 Adapter interruptions for QDIO
      67. 7.3.67 OSA Dynamic LAN idle
      68. 7.3.68 OSA Layer 3 virtual MAC for z/OS environments
      69. 7.3.69 QDIO Diagnostic Synchronization
      70. 7.3.70 Network Traffic Analyzer
      71. 7.3.71 Program-directed re-IPL
      72. 7.3.72 Coupling over InfiniBand and Integrated Coupling Adapter
      73. 7.3.73 Dynamic I/O support for InfiniBand and ICA CHPIDs
      74. 7.3.74 Simultaneous multithreading (SMT)
      75. 7.3.75 Single Instruction Multiple Data (SIMD)
    4. 7.4 Cryptographic support
      1. 7.4.1 CP Assist for Cryptographic Function
      2. 7.4.2 Crypto Express5S
      3. 7.4.3 Web deliverables
      4. 7.4.4 z/OS Integrated Cryptographic Service Facility (ICSF) FMIDs
      5. 7.4.5 ICSF migration considerations
    5. 7.5 GDPS Virtual Appliance
    6. 7.6 z/OS migration considerations
      1. 7.6.1 General guidelines
      2. 7.6.2 Hardware configuration definition
      3. 7.6.3 Coupling links
      4. 7.6.4 Large page support
      5. 7.6.5 Capacity Provisioning Manager
      6. 7.6.6 Decimal floating point and z/OS XL C/C++ considerations
    7. 7.7 IBM z Advanced Workload Analysis Reporter (zAware)
    8. 7.8 Coupling facility and CFCC considerations
    9. 7.9 Simultaneous multithreading (SMT)
    10. 7.10 Single-instruction multiple-data (SIMD)
    11. 7.11 The MIDAW facility
      1. 7.11.1 Modified Indirect Data Address Word (MIDAW) technical description
      2. 7.11.2 Extended format (EF) data sets
      3. 7.11.3 Performance benefits
    12. 7.12 IOCP
    13. 7.13 Worldwide port name (WWPN) tool
    14. 7.14 ICKDSF
    15. 7.15 IBM z BladeCenter Extension (zBX) Model 004 software support
      1. 7.15.1 IBM blades
      2. 7.15.2 IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise
    16. 7.16 Software licensing
      1. 7.16.1 Software licensing considerations
      2. 7.16.2 Monthly license charge (MLC) pricing metrics
      3. 7.16.3 Advanced Workload License Charges (AWLC)
      4. 7.16.4 z Systems International Program License Agreement (IPLA)
      5. 7.16.5 zBX licensed software
    17. 7.17 References
  12. Chapter 8. System upgrades
    1. 8.1 Upgrade types
      1. 8.1.1 Overview of upgrade types
      2. 8.1.2 Terminology that is related to CoD for z13 systems
      3. 8.1.3 Permanent upgrades
      4. 8.1.4 Temporary upgrades
    2. 8.2 Concurrent upgrades
      1. 8.2.1 Model upgrades
      2. 8.2.2 Customer Initiated Upgrade facility
      3. 8.2.3 Summary of concurrent upgrade functions
    3. 8.3 Miscellaneous equipment specification (MES) upgrades
      1. 8.3.1 MES upgrade for processors
      2. 8.3.2 MES upgrades for memory
      3. 8.3.3 MES upgrades for I/O
      4. 8.3.4 MES upgrades for the zBX
      5. 8.3.5 Summary of plan-ahead features
    4. 8.4 Permanent upgrade through the CIU facility
      1. 8.4.1 Ordering
      2. 8.4.2 Retrieval and activation
    5. 8.5 On/Off Capacity on Demand
      1. 8.5.1 Overview
      2. 8.5.2 Ordering
      3. 8.5.3 On/Off CoD testing
      4. 8.5.4 Activation and deactivation
      5. 8.5.5 Termination
      6. 8.5.6 z/OS capacity provisioning
    6. 8.6 Capacity for Planned Event (CPE)
    7. 8.7 Capacity Backup (CBU)
      1. 8.7.1 Ordering
      2. 8.7.2 CBU activation and deactivation
      3. 8.7.3 Automatic CBU enablement for GDPS
    8. 8.8 Nondisruptive upgrades
      1. 8.8.1 Components
      2. 8.8.2 Concurrent upgrade considerations
    9. 8.9 Summary of Capacity on Demand offerings
  13. Chapter 9. Reliability, availability, and serviceability
    1. 9.1 The RAS strategy
    2. 9.2 Technology change
    3. 9.3 Structure change
    4. 9.4 Reducing complexity
    5. 9.5 Reducing touches
    6. 9.6 z13 availability characteristics
    7. 9.7 z13 RAS functions
      1. 9.7.1 Scheduled outages
      2. 9.7.2 Unscheduled outages
    8. 9.8 z13 enhanced drawer availability (EDA)
      1. 9.8.1 EDA planning considerations
      2. 9.8.2 Enhanced drawer availability processing
    9. 9.9 z13 Enhanced Driver Maintenance (EDM)
    10. 9.10 RAS capability for the HMC and SE
    11. 9.11 RAS capability for zBX Mod 004
    12. 9.12 Considerations for PowerHA in zBX environment
    13. 9.13 IBM z Advanced Workload Analysis Reporter
    14. 9.14 RAS capability for Flash Express
  14. Chapter 10. Environmental requirements
    1. 10.1 z13 power and cooling
      1. 10.1.1 z13 new rear cover design for vectored air output
      2. 10.1.2 Power requirements and consumption
      3. 10.1.3 Cooling requirements
      4. 10.1.4 Internal Battery Feature (IBF)
      5. 10.1.5 Emergency power-off switch
    2. 10.2 z13 physical specifications
    3. 10.3 z13 physical planning
      1. 10.3.1 Raised floor or non-raised floor
      2. 10.3.2 Top Exit Power feature
      3. 10.3.3 Top Exit I/O Cabling feature
      4. 10.3.4 Weight distribution plate
      5. 10.3.5 Bolt-down kit for raised floor
      6. 10.3.6 Nonraised floor frame tie-down kit
      7. 10.3.7 Service clearance areas
    4. 10.4 Energy management
      1. 10.4.1 Power usage
      2. 10.4.2 Environmental monitoring
      3. 10.4.3 IBM Systems Director Active Energy Manager
      4. 10.4.4 Unified Resource Manager: Energy management
    5. 10.5 zBX environmental requirements
      1. 10.5.1 zBX configurations
      2. 10.5.2 zBX power components
      3. 10.5.3 zBX cooling
      4. 10.5.4 zBX physical specifications
  15. Chapter 11. Hardware Management Console and Support Elements
    1. 11.1 Introduction to the HMC and SE
    2. 11.2 HMC and SE enhancements and changes
      1. 11.2.1 New rack-mounted HMC
      2. 11.2.2 New Support Elements
      3. 11.2.3 New backup options of HMCs and primary SEs
      4. 11.2.4 SE driver support with the HMC driver
      5. 11.2.5 HMC feature codes
      6. 11.2.6 Tree Style User Interface and Classic Style User Interface
    3. 11.3 HMC and SE connectivity
      1. 11.3.1 Hardware prerequisite changes
      2. 11.3.2 TCP/IP Version 6 on the HMC and SE
      3. 11.3.3 Assigning addresses to the HMC and SE
    4. 11.4 Remote Support Facility (RSF)
      1. 11.4.1 Security characteristics
      2. 11.4.2 RSF connections to IBM and Enhanced IBM Service Support System
      3. 11.4.3 HMC and SE remote operations
    5. 11.5 HMC and SE key capabilities
      1. 11.5.1 Central processor complex (CPC) management
      2. 11.5.2 Logical partition management
      3. 11.5.3 Operating system communication
      4. 11.5.4 HMC and SE microcode
      5. 11.5.5 Monitoring
      6. 11.5.6 Capacity on demand (CoD) support
      7. 11.5.7 Features on Demand (FoD) support
      8. 11.5.8 Server Time Protocol (STP) support
      9. 11.5.9 NTP client and server support on the HMC
      10. 11.5.10 Security and user ID management
      11. 11.5.11 System Input/Output Configuration Analyzer on the SE and HMC
      12. 11.5.12 Automated operations
      13. 11.5.13 Cryptographic support
      14. 11.5.14 Installation support for z/VM using the HMC
    6. 11.6 HMC in an ensemble
      1. 11.6.1 Unified Resource Manager
      2. 11.6.2 Ensemble definition and management
      3. 11.6.3 HMC availability
      4. 11.6.4 Considerations for multiple HMCs
      5. 11.6.5 HMC browser session to a primary HMC
      6. 11.6.6 HMC ensemble topology
  16. Chapter 12. Performance
    1. 12.1 LSPR workload suite
    2. 12.2 Fundamental components of workload capacity performance
      1. 12.2.1 Instruction path length
      2. 12.2.2 Instruction complexity
      3. 12.2.3 Memory hierarchy and memory nest
    3. 12.3 Relative nest intensity
    4. 12.4 LSPR workload categories based on relative nest intensity
    5. 12.5 Relating production workloads to LSPR workloads
    6. 12.6 Workload performance variation
  17. Appendix A. IBM z Advanced Workload Analysis Reporter (IBM zAware)
    1. A.1 Troubleshooting in complex IT environments
    2. A.2 Introducing IBM zAware
    3. A.3 Understanding IBM zAware technology
    4. A.4 IBM zAware prerequisites
      1. 12.6.1 Feature on Demand (FoD)
    5. A.5 Configuring and using IBM zAware virtual appliance
  18. Appendix B. Channel options
  19. Appendix C. Flash Express
    1. C.1 Flash Express overview
    2. C.2 Using Flash Express
    3. C.3 Security on Flash Express
  20. Appendix D. GDPS Virtual Appliance
    1. D.1 GDPS overview
    2. D.2 Overview of GDPS Virtual Appliance
    3. D.3 GDPS Virtual Appliance recovery scenarios
  21. Appendix E. RDMA over Converged Ethernet (RoCE) improvements
    1. E.1 Overview
    2. E.2 Hardware
    3. E.3 Software exploitation of SMC-R
  22. Appendix F. IBM zEnterprise Data Compression Express
    1. F.1 Overview
    2. F.2 zEDC Express
    3. F.3 Software support
  23. Appendix G. Native Peripheral Component Interconnect Express (PCIe)
    1. G.1 Design of native PCIe I/O adapter management
    2. G.2 Native PCIe feature plugging rules
    3. G.3 Native PCIe feature definitions
  24. Related publications
    1. IBM Redbooks
    2. Other publications
    3. Online resources
    4. Help from IBM
  25. Back cover
  26. IBM System x Reference Architecture for Hadoop: IBM InfoSphere BigInsights Reference Architecture
    1. Introduction
    2. Business problem and business value
    3. Reference architecture use
    4. Requirements
    5. InfoSphere BigInsights predefined configuration
    6. InfoSphere BigInsights HBase predefined configuration
    7. Deployment considerations
    8. Customizing the predefined configurations
    9. Predefined configuration bill of materials
    10. References
    11. The team who wrote this paper
    12. Now you can become a published author, too!
    13. Stay connected to IBM Redbooks
  27. Notices
    1. Trademarks