IBM eServer zSeries 900 Technical Guide

48 IBM eServer zSeries 900 Technical Guide

The key point is that new Java and C/C++ applications require IEEE Floating Point and this

hardware implementation improves their performance for:

򐂰 Java floating-point operations

Former support was provided by software emulation. This new hardware enablement

optimizes performance while remaining compliant with the Java specification for

floating-point support.

򐂰 C/C++ programs

They are recompiled to allow usage of the additional floating-point registers.

2.5 Memory

As in the PU and MCM designs, the z900 memory design also provides great flexibility and

high availability, allowing:

򐂰 Concurrent Memory upgrades (except when physically installed capacity is reached)

The z900 servers may have more physically installed memory than the initial available

capacity. Memory upgrades within the physically installed capacity can be done

concurrently by the Licensed Internal Code and no hardware changes are required.

Concurrent memory upgrades can be done via Capacity Upgrade on Demand or

Customer Initiated Upgrade. Note that memory upgrades

cannot be done via Capacity

BackUp. See more details about concurrent upgrades in 6.1, “Concurrent upgrades” on

page 206.

򐂰 Dynamic Memory sparing

Memory cards are equipped with spare memory chips. During normal operations, the

system monitors and records accumulation of failing bits in memory chips that are

corrected by Error Correction Code (ECC). Before a failure threshold is reached that could

result in an uncorrectable error, the system invokes a spare memory chip in place of the

one with the accumulated failing bits. The z900 servers have enhanced the Dynamic

Memory sparing with up to 16 times more chips available for sparing. This dramatically

increases redundancy and virtually eliminates the need to replace a memory card due to a

DRAM failure.

򐂰 Partial Memory Restart

In the rare event of a memory card failure, Partial Memory Restart enables the system to

be restarted with half of the original memory. Processing can be resumed until a

replacement memory card is installed.

Memory error checking and correction code detects and corrects single bit errors, using the

Error Correction Code (ECC). Also, because of the memory structure design, errors due to a

single memory chip failure are corrected.

Storage background scrubbing provides continuous monitoring of storage for the correction of

detected faults before the storage is used.

The memory storage protect key design was enhanced by adding a third key array to each

memory card, improving the level of redundancy from 2 to 3. The Cache Level 1 (L1) delete

was also enhanced.

The memory cards use the latest fast 64 Mb Synchronous DRAMs. Storage Access is

interleaved between the storage cards and this tends to equalize storage activity across the

cards. Also, by separating the address and command from the data bus, contention is

reduced.