Chapter 1. zSeries 900 overview 5
Figure 1-2 z900 functions and features
1.3.1 Processor
MultiChip Module technology
The MultiChip Module (MCM) for the z900 is an approximately 5-inch-square ceramic
substrate (20 PU models) consisting of 101 layers of glass ceramic and six layers of thin film
wired with 1 km of wire. The PU chip is based on CMOS 8SE with copper interconnect and
Silicon-on-insulator (SOI) technologies on turbo models, or CMOS 8S with copper
interconnect technology on non-turbo models.
20-PU MCM
The 20-PU MCM is the technology cornerstone for the z900, from a 1-way up to a full 16-way
server. Combining up to 32 z900s in a Parallel Sysplex, installations can realize up to
512-way processing.
While present installations may employ a conglomerate of multiserver systems, the z900
offers the new paradigm of the Multi-System Server (see Figure 1-3 on page 6). The z900
models offer unparalleled flexibility to the enterprise in speedy deployment of e-business
solutions.
B Frame
(for IBF
feature)
Processor
64-bit Architecture
20 PUs (max 16 CPs) - Turbo & non-Turbo
CMOS 8SE or 8S Technology
Crypto Coprocessors (SCM on board, CMOS 7S)
MCU on all models
Capacity Upgrade on Demand
Capacity BackUp
Customer Initiated Upgrade
Memory
64-bit architecture
Maximum memory = 64 GB
Concurrent memory Upgrade
I/O
64-bit architecture (43/48-bit I/O addressing in H/W)
Up to 256 ESCON channels (16-port ESCON cards)
Up to 24 x 1GB/s STIs Links
Up to 96 2Gb/s FICON Express Channels:
FC (native), FCV (Bridge) or FCP modes
Up to 88 Parallel channels (96 on upgrade on RPQ)
FICON CTC
CHPID assignment function
I/O priority queuing
Dynamic CHPID management
Open systems
OSA-2 (FDDI, Token Ring)
OSA-Express (GbEthernet, ATM, Fast EN, Token Ring)
HiperSockets
PCICC and PCICA
FCP for Linux
Parallel Sysplex
Coupling Facility model
ISC-3, ICB-3, ICB-2, IC-3
System-Managed CF Structure Duplexing
Intelligent resource Director
Hardware System Structure
Primary Service Element
Alternate Service Element
PSCN 2000
Z Frame
A Frame

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