Chapter 15. Clocking
The Previous Chapter
The high speed signaling performed by HT devices is based on point-to-point differential signaling and source synchronous clocking. Details associated with link power requirements and the driver and receiver characteristics are discussed in this chapter. Also, the characteristics of the system-related signals, including RESET#, PWROK, LDTSTOP#, and LDTREQ# are discussed.
This Chapter
This chapter focuses on the source synchronous clocking environment within HT. This involves the use of the source synchronous transmit clock to load data into a receive FIFO and the transfer of data into the receiver time domain with a receive clock that unloads data from the FIFO. Additionally, the specification defines ...
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