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Hardware/Firmware Interface Design

Book Description

Why care about hardware/firmware interaction? These interfaces are critical, a solid hardware design married with adaptive firmware can access all the capabilities of an application and overcome limitations caused by poor communication. For the first time, a book has come along that will help hardware engineers and firmware engineers work together to mitigate or eliminate problems that occur when hardware and firmware are not optimally compatible. Solving these issues will save time and money, getting products to market sooner to create more revenue.

The principles and best practices presented in this book will prove to be a valuable resource for both hardware and firmware engineers. Topics include register layout, interrupts, timing and performance, aborts, and errors. Real world cases studies will help to solidify the principles and best practicies with an aim towards cleaner designs, shorter schedules, and better implementation!

  • Reduce product development delays with the best practices in this book
  • Concepts apply to ASICs, ASSPs, SoCs, and FPGAs
  • Real-world examples and case studies highlight the good and bad of design processes

Table of Contents

  1. Cover image
  2. Table of Contents
  3. Copyright
  4. Preface
  5. CHAPTER 1. Introduction
  6. 1.1. What Is the Hardware/Firmware Interface?
  7. 1.2. What Is a Best Practice?
  8. 1.3. “First Time Right” Also Means…
  9. 1.4. Target Audience
  10. 1.5. Project Life Cycle
  11. 1.6. Case Study
  12. 1.7. Summary
  13. CHAPTER 2. Principles
  14. 2.1. Seven Principles of Hardware/Firmware Interface Design
  15. 2.2. Summary
  16. CHAPTER 3. Collaboration
  17. 3.1. First Steps
  18. 3.2. Formal Collaboration
  19. 3.3. Informal Collaboration
  20. 3.4. Summary
  21. CHAPTER 4. Planning
  22. 4.1. Industry Standards
  23. 4.2. Common Version
  24. 4.3. Compatibility
  25. 4.4. Defects
  26. 4.5. Analysis
  27. 4.6. Postmortem
  28. 4.7. Summary
  29. CHAPTER 5. Documentation
  30. 5.1. Types
  31. 5.2. Document Management
  32. 5.3. Reviews
  33. 5.4. Content
  34. 5.5. Registers
  35. 5.6. Bits
  36. 5.7. Interrupts
  37. 5.8. Time
  38. 5.9. Errors
  39. 5.10. Information
  40. 5.11. Summary
  41. CHAPTER 6. Superblock
  42. 6.1. Benefits of a Superblock
  43. 6.2. Consolidation
  44. 6.3. I/O Signals
  45. 6.4. Parameterization
  46. 6.5. Summary
  47. CHAPTER 7. Design
  48. 7.1. Event Notification
  49. 7.2. Performance
  50. 7.3. Power-On
  51. 7.4. Communication and Control
  52. 7.5. Summary
  53. CHAPTER 8. Registers
  54. 8.1. Addressing
  55. 8.2. Bit Assignment
  56. 8.3. Data Types
  57. 8.4. Hardware Identification
  58. 8.5. Communication and Control
  59. 8.6. Summary
  60. CHAPTER 9. Interrupts
  61. 9.1. Design
  62. 9.2. Pending Register
  63. 9.3. Enable Register
  64. 9.4. Optional Registers
  65. 9.5. Interrupt Module Review
  66. 9.6. Triggering on Both Edges
  67. 9.7. Using the Interrupt Module
  68. 9.8. Summary
  69. CHAPTER 10. Aborts, etc.
  70. 10.1. Definitions
  71. 10.2. Halts
  72. 10.3. Resets
  73. 10.4. Aborts
  74. 10.5. Summary
  75. CHAPTER 11. Hooks
  76. 11.1. Designing for Hooks
  77. 11.2. Peek…
  78. 11.3. …And Poke
  79. 11.4. Monitor
  80. 11.5. More Hooks
  81. 11.6. Summary
  82. CHAPTER 12. Conclusion
  83. 12.1. Key Points
  84. 12.2. Benefits
  85. 12.3. Seven Principles of Hardware/Firmware Interface Design
  86. 12.4. It Finally Works! Let's Ship It!
  87. Appendix A. Best Practices
  88. Appendix B. Bicycle Controller Specification
  89. Glossary
  90. Index