Low-κ/CU Cleaning and Drying
Copper metal interconnects and porous low dielectric constant insulators have been chosen for integration schemes to reduce the resistivity and the capacitance delay in advanced IC devices. The use of these materials within the damascene integration schemes provides substantial challenges to effectively clean features after etching and chemical mechanical polishing. Plasmas etching and striping processes create residues and low-κ damage. Wet cleans can corrode copper and leave moisture and contaminants in the low-κ material. This chapter discusses the challenges and the presents solutions for post-etch stripping, cleaning, residue removal, and post-CMP processing for low-κ/copper interconnect structures. Using the optimum processing conditions and compatible cleaning chemistries are critical for prevention of the dielectric damage, corrosion, and particle removal, without detrimentally impacting the materials. Optimal wet and dry cleaning processes can effectively clean the surface of the remaining photoresist, post-etch residue while doing minimal damage. Chemical mechanical polishing processes require cleaning to remove slurry particles and to preclude oxidation of copper line structures. Pore sealing and dielectric ...