Future Trends in Microelectronics: Up the Nano Creek

Carbon-Nanotube Solutions for the Post-CMOS-Scaling World

P. M. Solomon

IBM Research, SRDC, T. J. Watson Research Center Yorktown Heights, NY 10598, U.S.A.

1.   Introduction

The CMOS research world has been up-ended in the past few years with the realization that the end of scaling is indeed approaching fast¹ and that other, more radical solutions need to be found. Much work has been focused on investigating a radical (for CMOS) set of new materials, strain engineering, and new geometries such as two-dimensional (2D) electrostatically confined structures and 3D heterogeneous integration. These approaches extend the technology and provide a more powerful end-point, but do not drastically alter the scaling scenarios. The capabilities projected for future CMOS are enormously larger than even today’s gigascale integrated circuit (IC) chips, so the question arises as to the need for any CMOS follow-on at all. An interesting feature, pertaining especially to the silicon-on-insulator (SOI) approaches, is that the “silicon” technology is becoming divorced from the bulk silicon material. Indeed, for these technologies any convenient material could, in principle, be used for the substrate.

Of the various alternative “nano-offerings” investigated in the past few years,^2,3 none can be seen as a serious competitor to ultimate CMOS. Device characteristics are poor, unreliable and noisy, and manufacturing methodologies are uncertain at best. A possible exception, at least in terms of the intrinsic ...