FSM-based Digital Design using Verilog HDL

9

Asynchronous Finite-State Machines

9.1 INTRODUCTION

Most FSM systems are synchronous; that is, they make use of a clock to move from one state to the next. Using a clock to control the synchronous movement between one state and the next allows the FSM logic time to settle before the next transition and, hence, overcomes some logic delay problems that may arise. For this reason, synchronous systems are, by far, the most popular in digital electronics; and most HDLs used to define them are optimized for synchronous system design.

However, there is another kind of FSM, one that does not use a clock to instigate a transition between states. This is knows as the asynchronous FSM. In an asynchronous FSM, the transition between states is controlled by the event inputs, so that the FSM does not need to wait for a clock signal input. For this reason, asynchronous FSM are sometimes called ‘event-driven’ FSMs.

A typical event FSM is shown in Figure 9.1. In this FSM, the transition from state s0 to s1 will take place when input s is logic 1 AND input c is logic 0. On reaching state s1, the FSM will remain in this state until the input c goes to logic 1, at which point it will move to state s2. Here, it will remain until input c goes to logic 0 to move to state s3, before returning to state s0 when input s goes to logic 0.

In this example, the FSM will only change state when there is a change of input variable; hence, the event nature of the system.

Sometimes, it is desired to change state ...