Key Features
Basic OCP
Master-slave interface with unidirectional signals
Driven and sampled by the rising edge of the OCP clock
Fully synchronous, no multicycle timing paths
All signals are strictly point-to-point (except clock and reset)
Simple request/acknowledge protocol
Supports data transfer on every clock cycle
Allows master or slave to control transfer rate
Configurable data word width
Configurable address width
Pipelined or blocking reads
Specific description formats for core characteristics, interfaces (signals, timing, and configuration), performance
Simple Extensions Enhance Performance
Burst codes link related transfers into complete transaction
Burst transactions supported:
Sequential (defined or undefined length)
Streaming (FIFO)
Core-specific ...
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