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FPGAs: World Class Designs

Book Description

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Clive "Max" Maxfield renowned author, columnist, and editor of PL DesignLine has selected the very best FPGA design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of FPGA design from design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving FPGA design problems and how to successfully apply theory to actual design tasks. The material has been selected for its timelessness as well as for its relevance to contemporary FPGA design issues.

Contents
Chapter 1 Alternative FPGA Architectures
Chapter 2 Design Techniques, Rules, and Guidelines
Chapter 3 A VHDL Primer: The Essentials
Chapter 4 Modeling Memories
Chapter 5 Introduction to Synchronous State Machine Design and Analysis
Chapter 6 Embedded Processors
Chapter 7 Digital Signal Processing
Chapter 8 Basics of Embedded Audio Processing
Chapter 9 Basics of Embedded Video and Image Processing
Chapter 10 Programming Streaming FPGA Applications Using Block Diagrams In Simulink
Chapter 11 Ladder and functional block programming
Chapter 12 Timers

*Hand-picked content selected by Clive "Max" Maxfield, character, luminary, columnist, and author
*Proven best design practices for FPGA development, verification, and low-power
*Case histories and design examples get you off and running on your current project

Table of Contents

  1. Brief Table of Contents
  2. Table of Contents
  3. Copyright
  4. Preface
  5. About the Editor
  6. About the Contributors
  7. Chapter 1. Alternative FPGA Architectures
    1. 1.1. A Word of Warning
    2. 1.2. A Little Background Information
    3. 1.3. Antifuse versus SRAM versus…
    4. 1.4. Fine-, Medium-, and Coarse-Grained Architectures
    5. 1.5. MUX- versus LUT-Based Logic Blocks
    6. 1.6. CLBs versus LABs versus Slices
    7. 1.7. Fast Carry Chains
    8. 1.8. Embedded RAMs
    9. 1.9. Embedded Multipliers, Adders, MACs, Etc
    10. 1.10. Embedded Processor Cores (Hard and Soft)
    11. 1.11. Clock Trees and Clock Managers
    12. 1.12. General-Purpose I/O
    13. 1.13. Gigabit Transceivers
    14. 1.14. Hard IP, Soft IP, and Firm IP
    15. 1.15. System Gates versus Real Gates
    16. 1.16. FPGA Years
  8. Chapter 2. Design Techniques, Rules, and Guidelines
    1. 2.1. Hardware Description Languages
    2. 2.2. Top-Down Design
    3. 2.3. Synchronous Design
    4. 2.4. Floating Nodes
    5. 2.5. Bus Contention
    6. 2.6. One-Hot State Encoding
    7. 2.7. Design For Test (DFT)
    8. 2.8. Testing Redundant Logic
    9. 2.9. Initializing State Machines
    10. 2.10. Observable Nodes
    11. 2.11. Scan Techniques
    12. 2.12. Built-In Self-Test (BIST)
    13. 2.13. Signature Analysis
    14. 2.14. Summary
  9. Chapter 3. A VHDL Primer
    1. 3.1. Introduction
    2. 3.2. Entity: Model Interface
    3. 3.3. Architecture: Model Behavior
    4. 3.4. Process: Basic Functional Unit in VHDL
    5. 3.5. Basic Variable Types and Operators
    6. 3.6. Decisions and Loops
    7. 3.7. Hierarchical Design
    8. 3.8. Debugging Models
    9. 3.9. Basic Data Types
    10. 3.10. Summary
  10. Chapter 4. Modeling Memories
    1. 4.1. Memory Arrays
    2. 4.2. Modeling Memory Functionality
    3. 4.3. VITAL_Memory Path Delays
    4. 4.4. VITAL_Memory Timing Constraints
    5. 4.5. Preloading Memories
    6. 4.6. Modeling Other Memory Types
    7. 4.7. Summary
  11. Chapter 5. Introduction to Synchronous State Machine Design and Analysis
    1. 5.1. Introduction
    2. 5.2. Models for Sequential Machines
    3. 5.3. The Fully Documented State Diagram
    4. 5.4. The Basic Memory Cells
    5. 5.5. Introduction to Flip-Flops
    6. 5.6. Procedure for FSM (Flip-Flop) Design and the Mapping Algorithm
    7. 5.7. The D Flip-Flops: General
    8. The RET D Flip-Flop
    9. The Master-Slave D Flip-Flop
    10. 5.8. Flip-Flop Conversion: The T, JK Flip-Flops and Miscellaneous Flip-Flops
    11. The JK Flip-Flops and Their Design from D Flip-Flops
    12. 5.9. Latches and Flip-Flops with Serious Timing Problems: A Warning
    13. 5.10. Asynchronous Preset and Clear Overrides
    14. 5.11. Setup and Hold Time Requirements of Flip-Flops
    15. 5.12. Design of Simple Synchronous State Machines with Edge-Triggered Flip-Flops: Map Conversion
    16. 5.13. Analysis of Simple State Machines
    17. 5.14. VHDL Description of Simple State Machines
    18. References
  12. Chapter 6. Embedded Processors
    1. 6.1. Introduction
    2. 6.2. A Simple Embedded Processor
    3. 6.3. Soft Core Processors on an FPGA
    4. 6.4. Summary
  13. Chapter 7. Digital Signal Processing
    1. 7.1. Overview
    2. 7.2. Basic DSP System
    3. 7.3. Essential DSP Terms
    4. 7.4. DSP Architectures
    5. 7.5. Parallel Execution in DSP Components
    6. 7.6. Parallel Execution in FPGA
    7. 7.7. When to Use FPGAs for DSP
    8. 7.8. FPGA DSP Design Considerations
    9. 7.9. FIR Filter Concept Example
    10. 7.10. Summary
  14. Chapter 8. Basics of Embedded Audio Processing
    1. 8.1. Introduction
    2. 8.2. Audio Sources and Sinks
    3. 8.3. Interconnections
    4. 8.4. Dynamic Range and Precision
    5. 8.5. Audio Processing Methods
    6. References
  15. Chapter 9. Basics of Embedded Video and Image Processing
    1. 9.1. Introduction
    2. 9.2. Broadcast TV—NTSC and PAL
    3. 9.3. Color Spaces
    4. 9.4. Digital Video
    5. 9.5. A Systems View of Video
    6. 9.6. Embedded Video Processing Considerations
    7. 9.7. Compression/Decompression
    8. References
  16. Chapter 10. Programming Streaming FPGA Applications Using Block Diagrams in Simulink
    1. 10.1. Designing High-Performance Datapaths using Stream-Based Operators
    2. 10.2. An Image-Processing Design Driver
    3. 10.3. Specifying Control in Simulink
    4. 10.4. Component Reuse: Libraries of Simple and Complex Subsystems
    5. 10.5. Summary
  17. BibliographyReferences
  18. Chapter 11. Ladder and Functional Block Programming
    1. 11.1. Ladder Diagrams
    2. 11.2. Logic Functions
    3. 11.3. Latching
    4. 11.4. Multiple Outputs
    5. 11.5. Entering Programs
    6. 11.6. Function Blocks
    7. 11.7. Program Examples
  19. Chapter 12. Timers
    1. 12.1. Types of Timers
    2. 12.2. Programming Timers
    3. 12.3. Off-Delay Timers
    4. 12.4. Pulse Timers
    5. 12.5. Programming Examples
  20. Index
    1. SYMBOL
    2. A
    3. B
    4. C
    5. D
    6. E
    7. F
    8. G
    9. H
    10. I
    11. J
    12. K
    13. L
    14. M
    15. N
    16. O
    17. P
    18. Q
    19. R
    20. S
    21. T
    22. U
    23. V
    24. W
    25. X
    26. Y