List of Figures
Figure 1-1. A simple programmable function.
Figure 1-2. Augmenting the device with unprogrammed fusible links.
Figure 1-3. Programmed fusible links.
Figure 1-4. Unprogrammed antifuse links.
Figure 1-5. Programmed antifuse links.
Figure 1-6. Growing an antifuse.
Figure 1-7. An SRAM-based programmable cell.
Figure 1-9. An EPROM transistor-based memory cell
Figure 1-8. Standard MOS versus EPROM transistors.
Figure 2-1. Underlying FPGA fabric.
Figure 2-2. MUX-based logic block.
Figure 2-3. A transmission gate-based LUT (programming chain omitted for purposes of clarity).
Figure 2-4. Required function and associated truth table.
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