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FPGAs: Instant Access by Clive Maxfield

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Chapter 4. FPGA vs. ASIC Designs

In an Instant

    • When You Switch from ASIC to FPGA Design, or Vice Versa
  • Coding Styles
  • Pipelining and Levels of Logic
    • Levels of Logic
  • Asynchronous Design Practices
    • Asynchronous Structures
    • Combinational Loops
    • Delay Chains
  • Clock Considerations
    • Clock Domains
    • Clock Balancing
    • Clock Gating versus Clock Enabling
    • PLLs and Clock Conditioning Circuitry
    • Reliable Data Transfer across Multiclock Domains
  • Register and Latch Considerations
    • Latches
    • Flip-flops with both “Set” and “Reset” Inputs
    • Global Resets and Initial Conditions
  • Resource Sharing (Time-Division Multiplexing)
    • Use It or Lose It!
    • But Wait, There's More
  • State Machine Encoding
  • Test Methodologies
  • Migrating ASIC Designs to FPGAs and Vice Versa
    • Alternative ...

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