The synthesis process generates many different types of files. Some will be used during the FPGA development process and others will have no meaning to you, see Figure 6-8. The synthesis process has done a lot of work to break down the high-level design to a lower level. At the completion of the synthesis phase the original design is closer to a format that will be used to program an FPGA.
Netlists, status reports and schematic views are some of the outputs generated by the synthesis tool that will help you during the development process.