FPGAs 101

Chapter 6. Synthesis

6.1. Introduction

Synthesis is the point in FGPA development where a high-level design is broken down into a mid-level netlist that is now associated with logic and internal FPGA resources. The design can be the one presented in this book or one you or someone else created or modified. It can be in several different formats—HDL, schematic capture, or a mixture—and may have been verified through simulation. In spite of whoever created or modified the design and the format, simulated or not, the design must be synthesized before it can be programmed into an FPGA.

Although, in this book, synthesis is performed following simulation, it could be performed immediately following the design phase. Once the design is complete it ...