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FPGAs 101 by Gina Smith

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4.8.1. Design Package

From the requirements specification, you have determined that your assignment is to develop VHDL firmware that will receive two pulses and determine if the pulses have valid pulse width and spacing. Pulse spacing corresponds to two modes, Mode 2 and Mode 3A. The modes are decoded for valid pulses only, (i.e., with correct spacing). To ensure consistency among all the firmware, signal names and font conventions have been provided in the design package.

Font Conventions
  • Capitalize the first letter of all reserved words.
  • Lower case user-defined signals and nonreserved words with underscores, for easier readability.
Inputs
  • The P1 and P3 pulse width is 0.8 μsec + 0.1 μsec, see Figure 4-8.
    • VHDL signal name is input_pulse ...

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