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FPGA-based Implementation of Signal Processing Systems, 2nd Edition

Book Description

An important working resource for engineers and researchers involved in the design, development, and implementation of signal processing systems

The last decade has seen a rapid expansion of the use of field programmable gate arrays (FPGAs) for a wide range of applications beyond traditional digital signal processing (DSP) systems. Written by a team of experts working at the leading edge of FPGA research and development, this second edition of FPGA-based Implementation of Signal Processing Systems has been extensively updated and revised to reflect the latest iterations of FPGA theory, applications, and technology. Written from a system-level perspective, it features expert discussions of contemporary methods and tools used in the design, optimization and implementation of DSP systems using programmable FPGA hardware. And it provides a wealth of practical insights—along with illustrative case studies and timely real-world examples—of critical concern to engineers working in the design and development of DSP systems for radio, telecommunications, audio-visual, and security applications, as well as bioinformatics, Big Data applications, and more. Inside you will find up-to-date coverage of:

  • FPGA solutions for Big Data Applications, especially as they apply to huge data sets
  • The use of ARM processors in FPGAs and the transfer of FPGAs towards heterogeneous computing platforms
  • The evolution of High Level Synthesis tools—including new sections on Xilinx's HLS Vivado tool flow and Altera's OpenCL approach
  • Developments in Graphical Processing Units (GPUs), which are rapidly replacing more traditional DSP systems

FPGA-based Implementation of Signal Processing Systems, 2nd Edition is an indispensable guide for engineers and researchers involved in the design and development of both traditional and cutting-edge data and signal processing systems. Senior-level electrical and computer engineering graduates studying signal processing or digital signal processing also will find this volume of great interest.

Table of Contents

  1. Preface
  2. List of Abbreviations
  3. 1 Introduction to Field Programmable Gate Arrays
    1. 1.1 Introduction
    2. 1.2 Field Programmable Gate Arrays
    3. 1.3 Influence of Programmability
    4. 1.4 Challenges of FPGAs
    5. Bibliography
  4. 2 DSP Basics
    1. 2.1 Introduction
    2. 2.2 Definition of DSP Systems
    3. 2.3 DSP Transformations
    4. 2.4 Filters
    5. 2.5 Adaptive Filtering
    6. 2.6 Final Comments
    7. Bibliography
  5. 3 Arithmetic Basics
    1. 3.1 Introduction
    2. 3.2 Number Representations
    3. 3.3 Arithmetic Operations
    4. 3.4 Alternative Number Representations
    5. 3.5 Division
    6. 3.6 Square Root
    7. 3.7 Fixed-Point versus Floating-Point
    8. 3.8 Conclusions
    9. Bibliography
  6. 4 Technology Review
    1. 4.1 Introduction
    2. 4.2 Implications of Technology Scaling
    3. 4.3 Architecture and Programmability
    4. 4.4 DSP Functionality Characteristics
    5. 4.5 Microprocessors
    6. 4.6 DSP Processors
    7. 4.7 Graphical Processing Units
    8. 4.8 System-on-Chip Solutions
    9. 4.9 Heterogeneous Computing Platforms
    10. 4.10 Conclusions
    11. Bibliography
  7. 5 Current FPGA Technologies
    1. 5.1 Introduction
    2. 5.2 Toward FPGAs
    3. 5.3 Altera Stratix® V and 10 FPGA Family
    4. 5.4 Xilinx UltrascaleTM/Virtex-7 FPGA families
    5. 5.5 Xilinx Zynq FPGA Family
    6. 5.6 Lattice iCE40isp FPGA Family
    7. 5.7 MicroSemi RTG4 FPGA Family
    8. 5.8 Design Stratregies for FPGA-based DSP Systems
    9. 5.9 Conclusions
    10. Bibliography
  8. 6 Detailed FPGA Implementation Techniques
    1. 6.1 Introduction
    2. 6.2 FPGA Functionality
    3. 6.3 Mapping to LUT-Based FPGA Technology
    4. 6.4 Fixed-Coefficient DSP
    5. 6.5 Distributed Arithmetic
    6. 6.6 Reduced-Coefficient Multiplier
    7. 6.7 Conclusions
    8. Bibliography
  9. 7 Synthesis Tools for FPGAs
    1. 7.1 Introduction
    2. 7.2 High-Level Synthesis
    3. 7.3 Xilinx Vivado
    4. 7.4 Control Logic Extraction Phase Example
    5. 7.5 Altera SDK for OpenCL
    6. 7.6 Other HLS Tools
    7. 7.7 Conclusions
    8. Bibliography
  10. 8 Architecture Derivation for FPGA-based DSP Systems
    1. 8.1 Introduction
    2. 8.2 DSP Algorithm Characteristics
    3. 8.3 DSP Algorithm Representations
    4. 8.4 Pipelining DSP Systems
    5. 8.5 Parallel Operation
    6. 8.6 Conclusions
    7. Bibliography
  11. 9 Complex DSP Core Design for FPGA
    1. 9.1 Introduction
    2. 9.2 Motivation for Design for Reuse
    3. 9.3 Intellectual Property Cores
    4. 9.4 Evolution of IP cores
    5. 9.5 Parameterizable (Soft) IP Cores
    6. 9.6 IP Core Integration
    7. 9.7 Current FPGA-based IP cores
    8. 9.8 Watermarking IP
    9. 9.9 Summary
    10. Bibliography
  12. 10 Advanced Model-Based FPGA Accelerator Design
    1. 10.1 Introduction
    2. 10.2 Dataflow Modeling of DSP Systems
    3. 10.3 Architectural Synthesis of Custom Circuit Accelerators from DFGs
    4. 10.4 Model-Based Development of Multi-Channel Dataflow Accelerators
    5. 10.5 Model-Based Development for Memory-Intensive Accelerators
    6. 10.6 Summary
    7. Notes
    8. Bibliography
  13. 11 Adaptive Beamformer Example
    1. 11.1 Introduction to Adaptive Beamforming
    2. 11.2 Generic Design Process
    3. 11.3 Algorithm to Architecture
    4. 11.4 Efficient Architecture Design
    5. 11.5 Generic QR Architecture
    6. 11.6 Retiming the Generic Architecture
    7. 11.7 Parameterizable QR Architecture
    8. 11.8 Generic Control
    9. 11.9 Beamformer Design Example
    10. 11.10 Summary
    11. Bibliography
  14. 12 FPGA Solutions for Big Data Applications
    1. 12.1 Introduction
    2. 12.2 Big Data
    3. 12.3 Big Data Analytics
    4. 12.4 Acceleration
    5. 12.5 k-Means Clustering FPGA Implementation
    6. 12.6 FPGA-Based Soft Processors
    7. 12.7 System Hardware
    8. 12.8 Conclusions
    9. Bibliography
  15. 13 Low-Power FPGA Implementation
    1. 13.1 Introduction
    2. 13.2 Sources of Power Consumption
    3. 13.3 FPGA Power Consumption
    4. 13.4 Power Consumption Reduction Techniques
    5. 13.5 Dynamic Voltage Scaling in FPGAs
    6. 13.6 Reduction in Switched Capacitance
    7. 13.7 Final Comments
    8. Bibliography
  16. 14 Conclusions
    1. 14.1 Introduction
    2. 14.2 Evolution in FPGA Design Approaches
    3. 14.3 Big Data and the Shift toward Computing
    4. 14.4 Programming Flow for FPGAs
    5. 14.5 Support for Floating-Point Arithmetic
    6. 14.6 Memory Architectures
    7. Bibliography
  17. Index
  18. EULA