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FPGA-based Implementation of Signal Processing Systems

Book Description

Field programmable gate arrays (FPGAs) are an increasingly popular technology for implementing digital signal processing (DSP) systems. By allowing designers to create circuit architectures developed for the specific applications, high levels of performance can be achieved for many DSP applications providing considerable improvements over conventional microprocessor and dedicated DSP processor solutions. The book addresses the key issue in this process specifically, the methods and tools needed for the design, optimization and implementation of DSP systems in programmable FPGA hardware. It presents a review of the leading-edge techniques in this field, analyzing advanced DSP-based design flows for both signal flow graph- (SFG-) based and dataflow-based implementation, system on chip (SoC) aspects, and future trends and challenges for FPGAs. The automation of the techniques for component architectural synthesis, computational models, and the reduction of energy consumption to help improve FPGA performance, are given in detail.

Written from a system level design perspective and with a DSP focus, the authors present many practical application examples of complex DSP implementation, involving:

  • high-performance computing e.g. matrix operations such as matrix multiplication;

  • high-speed filtering including finite impulse response (FIR) filters and wave digital filters (WDFs);

  • adaptive filtering e.g. recursive least squares (RLS) filtering;

  • transforms such as the fast Fourier transform (FFT).

FPGA-based Implementation of Signal Processing Systems is an important reference for practising engineers and researchers working on the design and development of DSP systems for radio, telecommunication, information, audio-visual and security applications. Senior level electrical and computer engineering graduates taking courses in signal processing or digital signal processing shall also find this volume of interest.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Dedication
  5. Contents
  6. About the Authors
    1. Roger Woods
    2. John McAllister
    3. Gaye Lightbody
    4. Ying Yi
  7. Preface
    1. DSP and FPGAs
    2. Audience
    3. Organization
  8. 1: Introduction to Field-programmable Gate Arrays
    1. 1.1 Introduction
    2. 1.2 A Short History of the Microchip
    3. 1.3 Influence of Programmability
    4. 1.4 Challenges of FPGAs
    5. References
  9. 2: DSP Fundamentals
    1. 2.1 Introduction
    2. 2.2 DSP System Basics
    3. 2.3 DSP System Definitions
    4. 2.4 DSP Transforms
    5. 2.5 Filter Structures
    6. 2.6 Adaptive Filtering
    7. 2.7 Basics of Adaptive Filtering
    8. 2.8 Conclusions
    9. References
  10. 3: Arithmetic Basics
    1. 3.1 Introduction
    2. 3.2 Number Systems
    3. 3.3 Fixed-point and Floating-point
    4. 3.4 Arithmetic Operations
    5. 3.5 Fixed-point versus Floating-point
    6. 3.6 Conclusions
    7. References
  11. 4: Technology Review
    1. 4.1 Introduction
    2. 4.2 Architecture and Programmability
    3. 4.3 DSP Functionality Characteristics
    4. 4.4 Processor Classification
    5. 4.5 Microprocessors
    6. 4.6 DSP Microprocessors (DSPμs)
    7. 4.7 Parallel Machines
    8. 4.8 Dedicated ASIC and FPGA Solutions
    9. 4.9 Conclusions
    10. References
  12. 5: Current FPGA Technologies
    1. 5.1 Introduction
    2. 5.2 Toward FPGAs
    3. 5.3 Altera FPGA Technologies
    4. 5.4 Xilinx FPGA Technologies
    5. 5.5 Lattice ® FPGA Families
    6. 5.6 Actel ® FPGA Technologies
    7. 5.7 Atmel ® FPGA Technologies
    8. 5.8 General Thoughts on FPGA Technologies
    9. References
  13. 6: Detailed FPGA Implementation Issues
    1. 6.1 Introduction
    2. 6.2 Various Forms of the LUT
    3. 6.3 Memory Availability
    4. 6.4 Fixed Coefficient Design Techniques
    5. 6.5 Distributed Arithmetic
    6. 6.6 Reduced Coefficient Multiplier
    7. 6.7 Final Statements
    8. References
  14. 7: Rapid DSP System Design Tools and Processes for FPGA
    1. 7.1 Introduction
    2. 7.2 The Evolution of FPGA System Design
    3. 7.3 Design Methodology Requirements for FPGA DSP
    4. 7.4 System Specification
    5. 7.5 IP Core Generation Tools for FPGA
    6. 7.6 System-level Design Tools for FPGA
    7. 7.7 Conclusion
    8. References
  15. 8: Architecture Derivation for FPGA-based DSP Systems
    1. 8.1 Introduction
    2. 8.2 DSP Algorithm Characteristics
    3. 8.3 DSP Algorithm Representations
    4. 8.4 Basics of Mapping DSP Systems onto FPGAs
    5. 8.5 Parallel Operation
    6. 8.6 Hardware Sharing
    7. 8.7 Application to FPGA
    8. 8.8 Conclusions
    9. References
  16. 9: The IRIS Behavioural Synthesis Tool
    1. 9.1 Introduction of Behavioural Synthesis Tools
    2. 9.2 IRIS Behavioural Synthesis Tool
    3. 9.3 IRIS Retiming
    4. 9.4 Hierarchical Design Methodology
    5. 9.5 Hardware Sharing Implementation (Scheduling Algorithm) for IRIS
    6. 9.6 Case Study: Adaptive Delayed Least-mean-squares Realization
    7. 9.7 Conclusions
    8. References
  17. 10: Complex DSP Core Design for FPGA
    1. 10.1 Motivation for Design for Reuse
    2. 10.2 Intellectual Property (IP) Cores
    3. 10.3 Evolution of IP Cores
    4. 10.4 Parameterizable (Soft) IP Cores
    5. 10.5 IP Core Integration
    6. 10.6 ADPCM IP Core Example
    7. 10.7 Current FPGA-based IP Cores
    8. 10.8 Summary
    9. References
  18. 11: Model-based Design for Heterogeneous FPGA
    1. 11.1 Introduction
    2. 11.2 Dataflow Modelling and Rapid Implementation for FPGA DSP Systems
    3. 11.3 Rapid Synthesis and Optimization of Embedded Software from DFGs
    4. 11.4 System-level Modelling for Heterogeneous Embedded DSP Systems
    5. 11.5 Pipelined Core Design of MADF Algorithms
    6. 11.6 System-level Design and Exploration of Dedicated Hardware Networks
    7. 11.7 Summary
    8. References
  19. 12: Adaptive Beamformer Example
    1. 12.1 Introduction to Adaptive Beamforming
    2. 12.2 Generic Design Process
    3. 12.3 Adaptive Beamforming Specification
    4. 12.4 Algorithm Development
    5. 12.5 Algorithm to Architecture
    6. 12.6 Efficient Architecture Design
    7. 12.7 Generic QR Architecture
    8. 12.8 Retiming the Generic Architecture
    9. 12.9 Parameterizable QR Architecture
    10. 12.10 Generic Control
    11. 12.11 Beamformer Design Example
    12. 12.12 Summary
    13. References
  20. 13: Low Power FPGA Implementation
    1. 13.1 Introduction
    2. 13.2 Sources of Power Consumption
    3. 13.3 Power Consumption Reduction Techniques
    4. 13.4 Voltage Scaling in FPGAs
    5. 13.5 Reduction in Switched Capacitance
    6. 13.6 Data Reordering
    7. 13.7 Fixed Coefficient Operation
    8. 13.8 Pipelining
    9. 13.9 Locality
    10. 13.10 Application to an FFT Implementation
    11. 13.11 Conclusions
    12. References
  21. 14: Final Statements
    1. 14.1 Introduction
    2. 14.2 Reconfigurable Systems
    3. 14.3 Memory Architectures
    4. 14.4 Support for Floating-point Arithmetic
    5. 14.5 Future Challenges for FPGAs
    6. References
  22. Index