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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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3.7   BENCHMARKING

One of the problems of the programmable logic area has been the lack of progress in developing credible methodologies for comparing architectures. In the absence of such methodologies, marketing departments have sprung in to fill the gap with a wide variety of benchmarks based around two main numbers, gate equivalents and utilization. This situation mirrors the somewhat checkered history of benchmarking conventional computers. A third class of benchmarks based around the use of silicon area has been proposed by academics, but no comparative data have been published as yet.

3.7.1   Utilization

Utilization is defined as the ratio of resources used to those provided to implement a particular design. For example, a design as implemented on a cellular array may use 50% of the available cell function units. High utilization is seen as a “good-thing,” indicating that the architecture efficiently supports the design. The principal advantage of this metric is that it is easy to calculate. There are several serious shortcomings, however.

  1. Utilization figures are influenced by the size of the box one draws around the design. If the box is measured in chip units, then the design may use a small percentage of the chip's resources simply because it is a small design. For this reason, one might suggest drawing the bounding box in terms of logic cell units. While this is certainly an improvement, it suffers from the drawback that designs that use special-purpose resources (e.g., ...

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