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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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3.6   PROGRAMMING

3.6.1   Technology

The main technologies used in the control store of FPGAs and programmable logic devices (PLDs) are as follows.

Static RAM The basic static RAM cell consists of two CMOS inverters connected in a loop to form a bistable device. The state of this device can be overwritten by external signals on the bit lines (marked B in Figures 3-18 and 3-19) via pass devices gated by the word lines (marked W). The sizes of the transistors are chosen to ensure that normal logic values on the bit lines can change the state of the cell (write cycle), but if an intermediate voltage is placed on the bit line, which is then left floating, the RAM cell itself can drive the bit line high or low according to its state (read cycle). In the case of the six-transistor RAM (Figure 3–18) true and complement values are applied to both sides of the RAM (effectively pushing and pulling it during a write), and in the five-transistor RAM (Figure 3–19) only one signal is applied (push only). Five-transistor RAMs are significantly more dense than six-transistor RAMs because less area is required to route bit and word lines through the array: they are also much harder to design and have less noise immunity. As process technology moves below 1 μm and with the move to 3-V power supplies, five-transistor RAM designs are being replaced by the more stable six-transistor cells.

The RAM cell is a storage device only, and in the FPGA application its Q output will control a separate (normally ...

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