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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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3.4   COMPUTATIONAL LOGIC ARRAYS

It is becoming apparent that the best method of increasing the speed of computation as we approach the speed limits of silicon technology is to increase parallelism. One problem with increasing parallelism is that computing structures consist of more than one resource. There are three classes—processor, memory, and communications. Different algorithms require different amounts of each resource, but to guarantee n times speedup, an n processor parallel computer must provide n times the limiting resource, that is, not only n processors but n times the memory and communications as well. While VLSI technology can provide increases in density each year it is not feasible to expect to increase performance on each of three independent axes while maintaining constant price. Parallel supercomputers will always be expensive.

Systolic and other VLSI design styles where processors are tailored to particular applications offer a way out of this problem. Since processors are specialized they can be much simpler and hence smaller and faster than general-purpose processors: thus one can have more of them at the same cost. Similarly memory and communication resources can be tailored for a given algorithm. Reconfigurable VLSI devices have the potential to provide the benefits of special-purpose processors to general-purpose computing devices.

Computational logic arrays consist of an array of rectangular cells covering the plane provided by the underlying silicon. ...

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