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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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3.3   STRUCTURED PROGRAMMABLE ARRAY LOGIC

Before examining structured PALs, we will look at a simpler concept, the programmable read-only memory (PROM) as applied to two-level programmable logic. The idea is simple: a lookup table with n inputs, m outputs, and 2n rows. The PROM is attractive because:

  1. Given the number of inputs and outputs, one can specify a given device before determining the actual logic function to be implemented. This is a powerful capability since it allows the PCB design to be started before the logic design is completed. It also allows for PROM design upgrades after the PCB design is finalized.
  2. The delay through the programmable device is constant and independent of the logic function implemented: again this is a powerful property, allowing (he separation of timing verification from logic design.
  3. The function of the device can be specified at a high level as a series of logic equations or as a truth table, allowing rapid design.

There are two major drawbacks with the PROM architecture that have prevented it from becoming dominant in the marketplace:

  1. Silicon area, and hence cost, and sometimes more importantly, package and board area, is determined by the number of product terms. There are 2n product terms in an n input PROM.
  2. Delay through a PROM is proportional to the number of product terms, and hence scales badly as the number of inputs increases.

For these reasons PROMs are only suited for those functions where it is necessary to completely decode ...

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