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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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8.4   CONFIGURABLE LOGIC ARRAYS AND PROTOTYPING BOARDS

In Chapter 6, we saw how regular arrays of FPGAs could provide a high-performance custom-computing environment. The Algotronix CHS2×4 board took advantage of an unusual feature of the CAL architecture, that is, chips can be cascaded in any of the four principal directions, without much concern to effects at chip boundaries.

8.4.1   The XESS RIPP Board

The RIPP is a PC-based reconfigurable system containing up to eight Altera FLEX 8000 FPGAs or I-CUBE FPIDs on a single card. The FPGAs and FPIDs can be used interchangeably, thus allowing the user to trade off logic and I/O resources for a given application. The RIPP also has four 512K × 8 RAMs for data storage and another FLEX FPGA, which manages the interfaces between the RIPP, the PC, and the external world.

Fundamental Components   The Altera FLEX81188 packs 12,000 logic gates into a 17 × 17 pin-grid array (PGA) package. So if all eight sockets are loaded with FPGAs, the RIPP can support applications needing up to ≈ 100,000 gates.

The IQ160 FPID described in more detail earlier in this chapter has a 160 × 160 crossbar architecture that can realize any interconnection pattern without the need for complex routing. Since the IQ160 and the FLEX81188 have roughly the same amount of I/O (160 pins versus 184 pins), a single socket can support either device via the use of an adapter.

RIPP Internal Architecture   The bussing arrangement that interconnects the eight RIPP sockets is ...

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