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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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5.4   RANDOM TESTING

For large systems, random testing is often a practical alternative to exhaustive, or case-by-case testing, and may be built into integrated circuits and systems.

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Figure 5–15. Equations for state machine: state encoding for decade counter, less-significant bits.

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Figure 5–16. Equations for state machine: state encoding for decade counter more-significant bits.

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Figure 5–17. CLB entries for decade counter.

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Figure 5–18. Configurable logic block array for 3-decade counter.

Input patterns may be readily generated with the LFSR method just described. Signature analysis is a technique for compressing the resulting output patterns into a short word whose final value indicates success or failure. While compression inevitably could allow some circuit failures to produce an identical signature, the risk is usually small.

We will take the 4-bit ripple adder described in Figure 5–4. Figure 5–21 shows the top-level schematic. Since there are eight input bits, along with carry-in, we will use a 9-bit pseudorandom number generator. To compress the four sum bits and the carry-out ...

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