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Event-Based Neuromorphic Systems

Book Description

Neuromorphic electronic engineering takes its inspiration from the functioning of nervous systems to build more power efficient electronic sensors and processors. Event-based neuromorphic systems are inspired by the brain's efficient data-driven communication design, which is key to its quick responses and remarkable capabilities. This cross-disciplinary text establishes how circuit building blocks are combined in architectures to construct complete systems. These include vision and auditory sensors as well as neuronal processing and learning circuits that implement models of nervous systems.

Techniques for building multi-chip scalable systems are considered throughout the book, including methods for dealing with transistor mismatch, extensive discussions of communication and interfacing, and making systems that operate in the real world. The book also provides historical context that helps relate the architectures and circuits to each other and that guides readers to the extensive literature. Chapters are written by founding experts and have been extensively edited for overall coherence.

This pioneering text is an indispensable resource for practicing neuromorphic electronic engineers, advanced electrical engineering and computer science students and researchers interested in neuromorphic systems.

Key features:

  • Summarises the latest design approaches, applications, and future challenges in the field of neuromorphic engineering.

  • Presents examples of practical applications of neuromorphic design principles.

  • Covers address-event communication, retinas, cochleas, locomotion, learning theory, neurons, synapses, floating gate circuits, hardware and software infrastructure, algorithms, and future challenges.

  • Table of Contents

    1. Coverpage
    2. Titlepage
    3. Copyright
    4. Dedication
    5. Contents
    6. List of Contributors
    7. Foreword
    8. Acknowledgments
    9. List of Abbreviations and Acronyms
    10. 1 Introduction
      1. 1.1 Origins and Historical Context
      2. 1.2 Building Useful Neuromorphic Systems
      3. References
    11. Part I UNDERSTANDING NEUROMORPHIC SYSTEMS
      1. 2 Communication
        1. 2.1 Introduction
        2. 2.2 Address-Event Representation
          1. 2.2.1 AER Encoders
          2. 2.2.2 Arbitration Mechanisms
          3. 2.2.3 Encoding Mechanisms
          4. 2.2.4 Multiple AER Endpoints
          5. 2.2.5 Address Mapping
          6. 2.2.6 Routing
        3. 2.3 Considerations for AER Link Design
          1. 2.3.1 Trade-off: Dynamic or Static Allocation
          2. 2.3.2 Trade-off: Arbitered Access or Collisions?
          3. 2.3.3 Trade-off: Queueing versus Dropping Spikes
          4. 2.3.4 Predicting Throughput Requirements
          5. 2.3.5 Design Trade-offs
        4. 2.4 The Evolution of AER Links
          1. 2.4.1 Single Sender, Single Receiver
          2. 2.4.2 Multiple Senders, Multiple Receivers
          3. 2.4.3 Parallel Signal Protocol
          4. 2.4.4 Word-Serial Addressing
          5. 2.4.5 Serial Differential Signaling
        5. 2.5 Discussion
        6. References
      2. 3 Silicon Retinas
        1. 3.1 Introduction
        2. 3.2 Biological Retinas
        3. 3.3 Silicon Retinas with Serial Analog Output
        4. 3.4 Asynchronous Event-Based Pixel Output Versus Synchronous Frames
        5. 3.5 AER Retinas
          1. 3.5.1 Dynamic Vision Sensor
          2. 3.5.2 Asynchronous Time-Based Image Sensor
          3. 3.5.3 Asynchronous Parvo–Magno Retina Model
          4. 3.5.4 Event-Based Intensity-Coding Imagers (Octopus and TTFS)
          5. 3.5.5 Spatial Contrast and Orientation Vision Sensor (VISe)
        6. 3.6 Silicon Retina Pixels
          1. 3.6.1 DVS Pixel
          2. 3.6.2 ATIS Pixel
          3. 3.6.3 VISe Pixel
          4. 3.6.4 Octopus Pixel
        7. 3.7 New Specifications for Silicon Retinas
          1. 3.7.1 DVS Response Uniformity
          2. 3.7.2 DVS Background Activity
          3. 3.7.3 DVS Dynamic Range
          4. 3.7.4 DVS Latency and Jitter
        8. 3.8 Discussion
        9. References
      3. 4 Silicon Cochleas
        1. 4.1 Introduction
        2. 4.2 Cochlea Architectures
          1. 4.2.1 Cascaded 1D
          2. 4.2.2 Basic 1D Silicon Cochlea
          3. 4.2.3 2D Architecture
          4. 4.2.4 The Resistive (Conductive) Network
          5. 4.2.5 The BM Resonators
          6. 4.2.6 The 2D Silicon Cochlea Model
          7. 4.2.7 Adding the Active Nonlinear Behavior of the OHCs
        3. 4.3 Spike-Based Cochleas
          1. 4.3.1 Q-control of AEREAR2 Filters
          2. 4.3.2 Applications: Spike-Based Auditory Processing
        4. 4.4 Tree Diagram
        5. 4.5 Discussion
        6. References
      4. 5 Locomotion Motor Control
        1. 5.1 Introduction
          1. 5.1.1 Determining Functional Biological Elements
          2. 5.1.2 Rhythmic Motor Patterns
        2. 5.2 Modeling Neural Circuits in Locomotor Control
          1. 5.2.1 Describing Locomotor Behavior
          2. 5.2.2 Fictive Analysis
          3. 5.2.3 Connection Models
          4. 5.2.4 Basic CPG Construction
          5. 5.2.5 Neuromorphic Architectures
        3. 5.3 Neuromorphic CPGs at Work
          1. 5.3.1 A Neuroprosthesis: Control of Locomotion in Vivo
          2. 5.3.2 Walking Robots
          3. 5.3.3 Modeling Intersegmental Coordination
        4. 5.4 Discussion
        5. References
      5. 6 Learning in Neuromorphic Systems
        1. 6.1 Introduction: Synaptic Connections, Memory, and Learning
        2. 6.2 Retaining Memories in Neuromorphic Hardware
          1. 6.2.1 The Problem of Memory Maintenance: Intuition
          2. 6.2.2 The Problem of Memory Maintenance: Quantitative Analysis
          3. 6.2.3 Solving the Problem of Memory Maintenance
        3. 6.3 Storing Memories in Neuromorphic Hardware
          1. 6.3.1 Synaptic Models for Learning
          2. 6.3.2 Implementing a Synaptic Model in Neuromorphic Hardware
        4. 6.4 Toward Associative Memories in Neuromorphic Hardware
          1. 6.4.1 Memory Retrieval in Attractor Neural Networks
          2. 6.4.2 Issues
        5. 6.5 Attractor States in a Neuromorphic Chip
          1. 6.5.1 Memory Retrieval
          2. 6.5.2 Learning Visual Stimuli in Real Time
        6. 6.6 Discussion
        7. References
    12. Part II BUILDING NEUROMORPHIC SYSTEMS
      1. 7 Silicon Neurons
        1. 7.1 Introduction
        2. 7.2 Silicon Neuron Circuit Blocks
          1. 7.2.1 Conductance Dynamics
          2. 7.2.2 Spike-Event Generation
          3. 7.2.3 Spiking Thresholds and Refractory Periods
          4. 7.2.4 Spike-Frequency Adaptation and Adaptive Thresholds
          5. 7.2.5 Axons and Dendritic Trees
          6. 7.2.6 Additional Useful Building Blocks
        3. 7.3 Silicon Neuron Implementations
          1. 7.3.1 Subthreshold Biophysically Realistic Models
          2. 7.3.2 Compact I&F Circuits for Event-Based Systems
          3. 7.3.3 Generalized I&F Neuron Circuits
          4. 7.3.4 Above Threshold, Accelerated-Time, and Switched-Capacitor Designs
        4. 7.4 Discussion
        5. References
      2. 8 Silicon Synapses
        1. 8.1 Introduction
        2. 8.2 Silicon Synapse Implementations
          1. 8.2.1 Non Conductance-Based Circuits
          2. 8.2.2 Conductance-Based Circuits
          3. 8.2.3 NMDA Synapse
        3. 8.3 Dynamic Plastic Synapses
          1. 8.3.1 Short-Term Plasticity
          2. 8.3.2 Long-Term Plasticity
        4. 8.4 Discussion
        5. References
      3. 9 Silicon Cochlea Building Blocks
        1. 9.1 Introduction
        2. 9.2 Voltage-Domain Second-Order Filter
          1. 9.2.1 Transconductance Amplifier
          2. 9.2.2 Second-Order Low-Pass Filter
          3. 9.2.3 Stability of the Filter
          4. 9.2.4 Stabilised Second-Order Low-Pass Filter
          5. 9.2.5 Differentiation
        3. 9.3 Current-Domain Second-Order Filter
          1. 9.3.1 The Translinear Loop
          2. 9.3.2 Second-Order Tau Cell Log-Domain Filter
        4. 9.4 Exponential Bias Generation
        5. 9.5 The Inner Hair Cell Model
        6. 9.6 Discussion
        7. References
      4. 10 Programmable and Configurable Analog Neuromorphic ICs
        1. 10.1 Introduction
        2. 10.2 Floating-Gate Circuit Basics
        3. 10.3 Floating-Gate Circuits Enabling Capacitive Circuits
        4. 10.4 Modifying Floating-Gate Charge
          1. 10.4.1 Electron Tunneling
          2. 10.4.2 pFET Hot-Electron Injection
        5. 10.5 Accurate Programming of Programmable Analog Devices
        6. 10.6 Scaling of Programmable Analog Approaches
        7. 10.7 Low-Power Analog Signal Processing
        8. 10.8 Low-Power Comparisons to Digital Approaches: Analog Computing in Memory
        9. 10.9 Analog Programming at Digital Complexity: Large-Scale Field Programmable Analog Arrays
        10. 10.10 Applications of Complex Analog Signal Processing
          1. 10.10.1 Analog Transform Imagers
          2. 10.10.2 Adaptive Filters and Classifiers
        11. 10.11 Discussion
        12. References
      5. 11 Bias Generator Circuits
        1. 11.1 Introduction
        2. 11.2 Bias Generator Circuits
          1. 11.2.1 Bootstrapped Current Mirror Master Bias Current Reference
          2. 11.2.2 Master Bias Power Supply Rejection Ratio (PSRR)
          3. 11.2.3 Stability of the Master Bias
          4. 11.2.4 Master Bias Startup and Power Control
          5. 11.2.5 Current Splitters: Obtaining a Digitally Controlled Fraction of the Master Current
          6. 11.2.6 Achieving Fine Monotonic Resolution of Bias Currents
          7. 11.2.7 Using Coarse–Fine Range Selection
          8. 11.2.8 Shifted-Source Biasing for Small Currents
          9. 11.2.9 Buffering and Bypass Decoupling of Individual Biases
          10. 11.2.10 A General Purpose Bias Buffer Circuit
          11. 11.2.11 Protecting Bias Splitter Currents from Parasitic Photocurrents
        3. 11.3 Overall Bias Generator Architecture Including External Controller
        4. 11.4 Typical Characteristics
        5. 11.5 Design Kits
        6. 11.6 Discussion
        7. References
      6. 12 On-Chip AER Communication Circuits
        1. 12.1 Introduction
          1. 12.1.1 Communication Cycle
          2. 12.1.2 Speedup in Communication
        2. 12.2 AER Transmitter Blocks
          1. 12.2.1 AER Circuits within a Pixel
          2. 12.2.2 Arbiter
          3. 12.2.3 Other AER Blocks
          4. 12.2.4 Combined Operation
        3. 12.3 AER Receiver Blocks
          1. 12.3.1 Chip-Level Handshaking Block
          2. 12.3.2 Decoder
          3. 12.3.3 Handshaking Circuits in Receiver Pixel
          4. 12.3.4 Pulse Extender Circuits
          5. 12.3.5 Receiver Array Peripheral Handshaking Circuits
        4. 12.4 Discussion
        5. References
      7. 13 Hardware Infrastructure
        1. 13.1 Introduction
          1. 13.1.1 Monitoring AER Events
          2. 13.1.2 Sequencing AER Events
          3. 13.1.3 Mapping AER Events
        2. 13.2 Hardware Infrastructure Boards for Small Systems
          1. 13.2.1 Silicon Cortex
          2. 13.2.2 Centralized Communication
          3. 13.2.3 Composable Architecture Solution
          4. 13.2.4 Daisy-Chain Architecture
          5. 13.2.5 Interfacing Boards using Serial AER
          6. 13.2.6 Reconfigurable Mesh-Grid Architecture
        3. 13.3 Medium-Scale Multichip Systems
          1. 13.3.1 Octopus Retina + IFAT
          2. 13.3.2 Multichip Orientation System
          3. 13.3.3 CAVIAR
        4. 13.4 FPGAs
        5. 13.5 Discussion
        6. References
      8. 14 Software Infrastructure
        1. 14.1 Introduction
          1. 14.1.1 Importance of Cross-Community Commonality
        2. 14.2 Chip and System Description Software
          1. 14.2.1 Extensible Markup Language
          2. 14.2.2 NeuroML
        3. 14.3 Configuration Software
        4. 14.4 Address Event Stream Handling Software
          1. 14.4.1 Field-Programmable Gate Arrays
          2. 14.4.2 Structure of AE Stream Handling Software
          3. 14.4.3 Bandwidth and Latency
          4. 14.4.4 Optimization
          5. 14.4.5 Application Programming Interface
          6. 14.4.6 Network Transport of AE Streams
        5. 14.5 Mapping Software
        6. 14.6 Software Examples
          1. 14.6.1 ChipDatabase – A System for Tuning Neuromorphic aVLSI Chips
          2. 14.6.2 Spike Toolbox
          3. 14.6.3 jAER
          4. 14.6.4 Python and PyNN
        7. 14.7 Discussion
        8. References
      9. 15 Algorithmic Processing of Event Streams
        1. 15.1 Introduction
        2. 15.2 Requirements for Software Infrastructure
          1. 15.2.1 Processing Latency
        3. 15.3 Embedded Implementations
        4. 15.4 Examples of Algorithms
          1. 15.4.1 Noise Reduction Filters
          2. 15.4.2 Time-Stamp Maps and Subsampling by Bit-Shifting Addresses
          3. 15.4.3 Event Labelers as Low-Level Feature Detectors
          4. 15.4.4 Visual Trackers
          5. 15.4.5 Event-Based Audio Processing
        5. 15.5 Discussion
        6. References
      10. 16 Towards Large-Scale Neuromorphic Systems
        1. 16.1 Introduction
        2. 16.2 Large-Scale System Examples
          1. 16.2.1 Spiking Neural Network Architecture
          2. 16.2.2 Hierarchical AER
          3. 16.2.3 Neurogrid
          4. 16.2.4 High Input Count Analog Neural Network System
        3. 16.3 Discussion
        4. References
      11. 17 The Brain as Potential Technology
        1. 17.1 Introduction
        2. 17.2 The Nature of Neuronal Computation: Principles of Brain Technology
        3. 17.3 Approaches to Understanding Brains
        4. 17.4 Some Principles of Brain Construction and Function
        5. 17.5 An Example Model of Neural Circuit Processing
        6. 17.6 Toward Neuromorphic Cognition
        7. References
    13. Index