Essential Electronic Design Automation (EDA)

Summary

FE chip designers enter use design capture tools to enter their logic design ideas into the computer. These tools support block diagrams, schematic diagrams, or hardware description languages. The output is a netlist of logic gates and interconnecting wires.

Simulator tools verify the design using the netlist and test patterns developed by the design engineer. Test bench tools assist the test generation work. There are several kinds of simulators and simulation accelerators. As chips grow more complex, it takes more compute power to simulate them in a reasonable time.

Formal verification can catch some design errors by checking for the design intent. Static timing analyzer tools can check for timing errors more quickly than simulation. ...